HY27SS08561M Hynix Semiconductor, HY27SS08561M Datasheet - Page 14

• Manufacturer Part Number: HY27SS08561M
• Description: 256mbit 32mx8bit / 16mx16bit Nand Flash
• Manufacturer: Hynix Semiconductor

Read Memory Array
Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section.
Once the area (main or spare) has been selected using the Read A, Read B or Read C commands, three bus cycles are
required to input the address(refer to Table 3 and 4) of the data to be read.
The device defaults to Read A mode after powerup or a Reset operation. Devices, where page0 is read automatically at
power-up, are available on request.
When reading the spare area addresses:
are used to set the start address of the spare area while addresses:
are ignored.
Once the Read A or Read C commands have been issued they do not need to be reissued for subsequent read opera-
tions as the pointer remains in the respective area. However, the Read B command is effective for only one operation,
once an operation has been executed in Area B the pointer returns automatically to Area A and so another Read B
command is required to start another read operation in Area B.
Once a read command is issued three types of operations are available: Random Read, Page Read and Sequential Row
Read.
Random Read
Each time the command is issued the first read is Random Read.
Page Read
After the Random Read access the page data is transferred to the Page Buffer in a time of t
value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially
(from selected column address to last column address) by pulsing the Read Enable signal.
Sequential Row Read
After the data in last column of the page is output, if the Read Enable signal is pulsed and Chip Enable remains Low
then the next page is automatically loaded into the Page Buffer and the read operation continues. A Sequential Row
Read operation can only be used to read within a block. If the block changes a new read command must be issued.
Refer to Figures 12 and 13 for details of Sequential Row Read operations. To terminate a Sequential Row Read opera-
tion set the Chip Enable signal to High for more than t
row read option is disabled.
Rev 0.7 / Oct. 2004
- A0 to A3 (x8 devices)
- A0 to A2 (x16 devices)
- A4 to A7 (x8 devices)
- A3 to A7 (x16 devices)
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
EHEL
. Sequential Row Read is not available when the Sequential
HY27US(08/16)561M Series
HY27SS(08/16)561M Series
WHBH
(refer to Table 15 for
14