HY27SS08561M Hynix Semiconductor, HY27SS08561M Datasheet - Page 22

• Manufacturer Part Number: HY27SS08561M
• Description: 256mbit 32mx8bit / 16mx16bit Nand Flash
• Manufacturer: Hynix Semiconductor

Automatic Page 0 Read Description.
At powerup, once the supply voltage has reached the threshold level, V
state and the internal NAND device functions (reading, writing, erasing) are enabled.
The device then automatically switches to read mode where, as in any read operation, the device is busy for a time
t
goes High. The data can then be read out sequentially on the I/O bus by pulsing the Read Enable, R, signal. Figures 18
and 19 show the power-up waveforms for devices featuring the Automatic Page 0 Read option.
Sequential Row Read Disabled
If the device is delivered with sequential row read disabled and Automatic Read page0 at Power-up, only the first page
(page0) will be automatically read after the power-on sequence. Refer to Figure 18.
Sequential Row Read Enabled
If the device is delivered with the Automatic Page 0 Read option only (Sequential Row Read Enabled), the device will
automatically enter Sequential Row Read mode after the power-up sequence, and start reading Page 0, Page 1, etc.,
until the last memory location is reached, each new page being accessed after a time t
The Sequential Row Read operation can be inhibited or interrupted by de-asserting CE (set to V
mand. Refer to Figure 19.
Note: (1). V
Rev 0.7 / Oct. 2004
Vccth (1)
BLBH1
Vcc
RB
WE
CLE
RE
CE
ALE
I/O
during which data is transferred to the Page Buffer. Once the data transfer is complete the Ready/Busy signal
CCth
Figure 18. Sequential Row Read Disabled and Automatic Page 0 Read at power-up
is equal to 2.0V for 3.3V and to 1.5V for 1.8V Power Supply devices.
Busy
tBLBH1
Data
from Address N to Last Byte or Word in Page
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
N
Data
N+1
Data Output
Data
CCth
N+2
HY27US(08/16)561M Series
HY27SS(08/16)561M Series
, all digital outputs revert to their reset
BLBH1
.
IH
Data
Last
) or by issuing a com-
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