FIN3385 Fairchild Semiconductor, FIN3385 Datasheet - Page 7

• Manufacturer Part Number: FIN3385
• Description: Fin3385 * Fin3383 * Fin3384 * Fin3386 Low Voltage 28-bit Flat Panel Display Link Serializers/deserializers
• Manufacturer: Fairchild Semiconductor

t
t
t
t
t
t
LVDS Transmitter Timing Characteristics
t
t
t
t
t
t
Transmitter Output Data Jitter (f
t
t
t
t
t
t
t
Transmitter Output Data Jitter (f
t
t
t
t
t
t
t
Transmitter Output Data Jitter (f
t
t
t
t
t
t
t
t
t
Transmitter AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after V
Power-Down pin is above 1.5V.
Note 14: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 14). Figure 16 shows the skew
between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
TCP
TCH
TCL
CLKT
JIT
XIT
TLH
THL
STC
HTC
TPDD
TCCD
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
JCC
TPLLS
Symbol
Transmit Clock Period
Transmit Clock (TxCLKIn) HIGH Time
Transmit Clock Low Time
TxCLKIn Transition Time (Rising and Failing)
TxCLKIn Cycle-to-Cycle Jitter
TxIn Transition Time
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
TxIn Setup to TxCLNIn
TxIn Holds to TCLKIn
Transmitter Power-Down Delay
Transmitter Clock Input to Clock Output Delay
Transmitter Clock Input to Clock Output Delay
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
FIN3385 Transmitter Clock Out Jitter
(Cycle-to-Cycle)
See Figure 20
Transmitter Phase Lock Loop Set Time (Note 15)
Parameter
40 MHz) (Note 14)
65 MHz) (Note 14)
85 MHz) (Note 14)
See Figure 5
(10% to 90%) See Figure 6
See Figure 4
See Figure 5 (f
See Figure 12, (Note 13)
(T
See Figure 9
See Figure 16
See Figure 16
See Figure 16
f
f
f
See Figure 22, (Note 14)
a
a
a
A
7
40 MHz
65 MHz
85 MHz
25
f x 7
f x 7
f x 7
Test Conditions
q
C and with V
1
1
1
85 MHz)
CC
3.3V)
2a
3a
4a
5a
6a
a
2a
3a
4a
5a
6a
2a
3a
4a
5a
6a
11.76

a
a
0.35
0.35



Min
1.0
1.5
2.5
2.8
0.25







0.25
0.2





0.2





0
0.25
0.25
0.25
0.25
0.25
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.75
0.75
Typ
350
210
110
0.5
0.5
2a
3a
4a
5a
6a
2a
3a
4a
5a
6a
2a
3a
4a
5a
6a
T
0
a
0
a
0
a
www.fairchildsemi.com
CC
2a
3a
4a
5a
6a
a
2a
3a
4a
5a
6a
2a
3a
4a
5a
6a
a
a
reaches 3V and
Max
50.0
0.65
0.65
0.25

10.0
100
370
230
150
6.0
3.0
6.0
1.5
1.5
5.5
6.8





0.2

0.2

0.25










0.25
0.25
0.25
0.25
0.25
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
T
T