FIN3385 Fairchild Semiconductor, FIN3385 Datasheet - Page 9

• Manufacturer Part Number: FIN3385
• Description: Fin3385 * Fin3383 * Fin3384 * Fin3386 Low Voltage 28-bit Flat Panel Display Link Serializers/deserializers
• Manufacturer: Fairchild Semiconductor

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Receiver AC Electrical Characteristics (66MHz)
Note 20: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock ref-
erence point is the time when the clock falling edge passes through 2V. For hold time t
through
Note 21: Total channel latency from Sewrializer to deserializer is (T
Note 22: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
RCOP
RCOL
RCOH
RSRC
RHRC
RCOL
RCOH
RSRC
RHRC
ROLH
ROHL
RCCD
RPDD
RSPB0
RSPB1
RSPB2
RSPB3
RSPB4
RSPB5
RSPB6
RSPB0
RSPB1
RSPB2
RSPB3
RSPB4
RSPB5
RSPB6
RSKM
RPLLS
Symbol

0.8V.
Receiver Clock Output (RxCLKOut) Period
RxCLKOut LOW Time
RxCLKOut HIGH Time
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
RxCLKOut LOW Time
RxCLKOut HIGH Time
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Receiver Clock Input to Clock Output Delay
Receiver Power-Down Delay
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
RxIn Skew Margin
See Figure 17, (Note 22)
Receiver Phase Lock Loop Set Time
Parameter

t
TCCD
)
See Figure 8
See Figure 8
(Rising Edge Strobe)
(f
See Figure 8, (Note 20)
(Rising Edge Strobe)
(f
C
See Figure 8
See Figure 10, (Note 21)
T
See Figure 13
See Figure 17
(f
See Figure 17
(f
f
f
See Figure 11

A
L
9
(2*T
40 MHz
66 MHz
40 MHz)
66 MHz)
40 MHz)
65 MHz)
8 pF, (Note 20)
25

q
Test Conditions
C and V
t
RCCD
RHRC
). There is the clock period.
, the clock reference point is the time when falling edge passes
CC
3.3V
15.0
10.0
10.0
15.1
18.8
22.5
13.9
Min
11.6
11.7
490
400
6.5
6.0
5.0
5.0
4.5
4.0
3.5
1.0
4.5
8.1
0.7
2.9
5.1
7.3
9.5
11.0
12.2
11.6
11.6
11.9
15.6
19.2
22.9
12.1
14.3
Typ
6.3
7.6
7.3
6.3
2.0
1.8
5.0
1.4
5.0
8.5
1.1
3.3
5.5
7.7
9.9
T
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Max
50.0
2.15
9.15
12.6
16.3
19.9
23.6
10.2
12.4
14.6
10.0
9.0
9.0
5.0
5.0
7.5
1.0
5.8
1.4
3.6
5.8
8.0
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
P
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
s