FIN24AC Fairchild Semiconductor, FIN24AC Datasheet - Page 18
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FIN24AC
Manufacturer Part Number
FIN24AC
Description
Fin24ac ? ?serdes? 22-bit Bi-directional Serializer/deserializer
Manufacturer
Fairchild Semiconductor
Datasheet
1.FIN24AC.pdf
(25 pages)
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© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
AC Loading and Waveforms
The “worst-case” test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference
frequency, unless otherwise specified. Maximum power is measured at the maximum V
Typical values are measured at V
Note:
Figure 14. Differential CTL Output DC Test Circuit
Figure 17. CTL Output Load and Transition Times
DP[1:12]
CKREF
CKS0+
CKS0-
Input
DS+
DS-
V
DIFF
b
13
t
TLH
b
14
20%
666h
V
+
–
DIFF
b
0
1
= (DS+) – (DS-)
80%
DD
b
1
2
DS+
= 2.5V.
DS-
5 pF
b
80%
0
6
Figure 16. “Worst-Case” Serializer Test Pattern
DS+
R
R
DS-
L
L
/2
/2
b
1
7
100Ω
20%
b
0
8
V
t
THL
OS
T
999h
V
OD
b
0
11
b
1
12
18
b
1
1
Figure 15. CTL Input Common Mode Test Circuit
DD
b
0
2
DUT
values. Minimum values are measured at the minimum V
DPn
t
ROLH
Figure 18. LVCMOS Output Load
b
20%
1
6
+
–
b
and Transition Times
0
7
80%
100Ω Termination
b
1
8
DPn
666h
5pF
80%
b
1
11
DUT
b
0
12
1000Ω
20%
t
+
–
ROHL
b
1
+
–
www.fairchildsemi.com
VGO
b
2
DD
values.