DSPIC30F3011 Microchip Technology Inc., DSPIC30F3011 Datasheet - Page 143

• Manufacturer Part Number: DSPIC30F3011
• Description: Dspic30f3010/3011 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

20.3
The dsPIC30F3010/3011 differentiates between various
kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 20-2:
20.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally
characteristics must meet specified starting voltage
and rise rate requirements. The POR pulse will reset a
POR timer and place the device in the Reset state. The
POR also selects the device clock source identified by
the oscillator configuration fuses.
© 2007 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset cause by trap lockup (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an address pointer
(IOPUWR)
MCLR
V
Illegal Opcode/
Uninitialized W Register
DD
Reset
DD
Instruction
RESET
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
1.85V.
TRAP Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
The
RESET SYSTEM BLOCK DIAGRAM
Rise
device
BOREN
Glitch Filter
Digital
POR
supply
POR
), which is
BOR
voltage
Confidential
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 20-5. These bits
are used in software to determine the nature of the
Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 20-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected power-
up time-out (T
is based on device Configuration bits and can be 0 ms
(no delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up T
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
dsPIC30F3010/3011
PWRT
POR
) is applied. The T
S
R
+ T
PWRT
Q
. When these delays
DS70141D-page 141
PWRT
SYSRST
POR
parameter
, which is