DSPIC30F3011 Microchip Technology Inc., DSPIC30F3011 Datasheet - Page 81
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
DSPIC30F3011
Manufacturer Part Number
DSPIC30F3011
Description
Dspic30f3010/3011 Enhanced Flash 16-bit Digital Signal Controller
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC30F3011.pdf
(220 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
DSPIC30F3011-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3011-30I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
DSPIC30F3011-30I/P
Manufacturer:
Microchip
Quantity:
927
Company:
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
MICROCHIP
Quantity:
316
Company:
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
Company:
Part Number:
DSPIC30F3011T-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
DSPIC30F3011T-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3011T-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
12.2.2
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the interrupt
mode selected by the ICI<1:0> bits are applicable, as
well as the 4:1 and 16:1 capture prescale settings,
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover, the
ICSIDL bit must be asserted to a logic ‘0’.
If the input capture module is defined as ICM<2:0> = 111
in CPU Idle mode, the input capture pin will serve only as
an external interrupt pin.
© 2007 Microchip Technology Inc.
INPUT CAPTURE IN CPU IDLE
MODE
Confidential
12.3
The input capture channels have the ability to generate
an interrupt, based upon the selected number of
capture events. The selection number is set by control
bits ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx status register.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
Capture Interrupt Enable bit is located in the
corresponding IEC control register.
dsPIC30F3010/3011
Input Capture Interrupts
DS70141D-page 79