S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 47

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
The second byte the host sends is the base register index. The host then sends the data. The S5D2650
increments the index automatically after each byte of data is sent. Therefore, the host can write multiple bytes to
the slave if they are in sequential order. The host completes the transfer cycle with a STOP signal which is a LOW
to HIGH transition when the SCLK is high.
Each byte transfer consists of 9 clocks. When writing to the S5D2650, an acknowledge signal is asserted by the
salve device during the 9th clock.
A read cycle takes two START-STOP phases. The first phase is a write to the index register. The second phase is
the read from the data register.
The host initiates the first phase by sending the START signal. It then sends the slave device ID along with a 0 in
the R/W position. The index is then sent followed by the STOP signal.
The second phase also starts with the START signal. It then sends the slave device ID but with a 1 in the R/W
position to indicate data is to be read from the slave device. The host uses the SCLK to shift data out from the
S5D2650. A typical second phase in a read transaction is depicted in Figure 40. Auto index increment is supported
in Read mode.
SCLK
SDAT
ELECTRONICS
START
SCLK
SDAT
SCLK
SDAT
device ID
START
START
device ID
device ID
Figure 39.
Figure 40.
ACK
ACK
index
IIC Data Write
IIC Data Read
data
index
ACK
data
NACK
ACK
STOP
STOP
MULTIMEDIA VIDEO
data
ACK
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STOP
7/18/03