S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 86

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
Index
0x3F
CBWI
TASKB
REGUD
UVDLSL
UVDLEN
EVAVY
VIPMODE
CTRAPFSC
Mnemonic
CMDF
ELECTRONICS
Chroma bandwidth increase. This function should be used for digital video input mode only.
0
1
Select between task A and B as described in “VIP Specification V. 1.0”.
0
1
Control register update control.
0
1
U or V delay control when UVDLEN is set to 1.
0
1
Enable the function of UVDLSL.
0
1
Control the output of INVALY, INVALU, and INVALV codes when EVAV is inactive.
0
1
Allows transfer of hardware sliced VBI data as ancillary data during the following line’s
horizontal blanking period.
0
1
Enable chroma trap location based on Fsc frequency instead of field rate.
0
1
CTRAPFSC
bit 7
Normal chroma bandwidth.*
Increased chroma bandwidth.
Select CCIR 656 timing codes (T-bit is always 1).*
Select between task A and B when VBI data is output. If active video is output, T-bit
is set to 1(task A). If VBI data is output, T-bit is set to 0 (task B).
Registers are updated immediately after being written to.*
The following registers and register bits are updated only during the start of vertical
sync after they are written to:
Index 0x02, indices 0x17 through 0x1D, bit 0 of index 0x04, bits [2:0] and [6:4] of
index 0x0E.
V is delayed by 1 CK period.*
U is delayed by 1 CK period.
UVDLSL is disabled.*
UVDLSL is enabled.
Output of these codes are not affected by EVAV.*
These codes are output when EVAV is inactive (line is being dropped by the vertical
scaler).
Standard S5D2650 original sliced VBI data transfer.*
Optional ancillary sliced VBI data transfer.
Chroma trap based on field rate.*
Chroma trap based on detected Fsc frequency.
VIPMODE
bit 6
Command Register F
EVAVY
bit 5
UVDLEN
bit 4
UVDLSL
bit 3
REGUD
bit 2
MULTIMEDIA VIDEO
TASKB
bit 1
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CBWI
bit 0
7/18/03