S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 53

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
Index
TSTGEN
TSTGFR[1:0]
TSTGPH
TSTGPK
TSTGE1
VMEN
03h
Mnemonic
CMDC
ELECTRONICS
Enable manual control of horizontal phase and frequency tracking.
0
1
When TSTGEN == 1, these two bits control the horizontal frequency tracking.
00
01
1X
When TSTGEN == 1, this bit controls the horizontal phase tracking.
0
1
If TSTGE1 == 1, this bit controls AGC.
0
1
Enables the function of TSTGPK.
0
1
Vertical master mode.
0
1
VMEN
bit 7
Auto phase and frequency tracking.*
Enable manual control of horizontal phase and frequency with TSTGFR[1:0] and
TSTGPH.
Stop frequency tracking and freeze the frequency at the current value.*
Horizontal frequency tracks the input.
Horizontal frequency tracking ignores video input and runs at nominal value based
on the field rate and output pixel rate selected by IFMT and PIXEL bits.
No phase tracking.*
Horizontal phase tracks the input video or HS1 input if in slave mode.
AGC clamps to back porch and gain is set based on sync tip-back porch difference.*
AGC clamps to sync tip and gain is set based on peak-valley difference.
Disables TSTGPK.*
Enables TSTGPK.
Normal vertical sync operation.*
Vertical sync ignores input and free runs at 50 Hz or 60 Hz. This mode can be used
to generate video timing for a slave device.
TSTGE1
bit 6
Control register C
bit 5
0
TSTGPK TSTGPH
bit 4
bit 3
bit 2
TSTGFR[1:0]
MULTIMEDIA VIDEO
bit 1
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TSTGEN
bit 0
7/18/03