S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 56

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
Index
Index
Index
HS1E[8:1] -
HS1BE0
HS2B[8:1] -
HS2BE0
HS2E[8:1] -
HS2BE0
0Ch
0Ch
0Ah
0Ch
08h
09h
Mnemonic
Mnemonic
Mnemonic
HXTRA
HXTRA
HXTRA
HS2B
HS2E
HS1E
ELECTRONICS
If HS1 is programmed as an output, this 9-bit register defines the end location of the HS1
signal. The content of this register is a 2’s complement number which is used as an offset to the
default. The resolution for this register is 1 CK clock.
This 9-bit register defines the start location of the HS2 signal. The content of this register is a
2’s complement number which is used as an offset to the default HS2B location. The resolution
for this register is 1 CK clock.
This 9-bit register defines the end location of the HS2 signal. The content of this register is a 2’s
complement number which is used as an offset to the default HS2E location. The resolution for
this register is 1 CK clock.
bit 7
bit 7
bit 7
HAVB[10:8]
HAVB[10:8]
HAVB[10:8]
bit 6
bit 6
bit 6
HS2 Start Control
HS1 End Control
HS2 End Control
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
HS1E[8:1]
HS2B[8:1]
HS2E[8:1]
HAVE[10:8]
HAVE[10:8]
HAVE[10:8]
bit 3
bit 3
bit 3
bit 2
bit 2
bit 2
MULTIMEDIA VIDEO
HS1BE0 HS2BE0
HS1BE0 HS2BE0
HS1BE0 HS2BE0
bit 1
bit 1
bit 1
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bit 0
bit 0
bit 0
7/18/03