S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 54

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
Index
GPPORT
PROG
SYNDIR
INPSL[1:0]
CKDIR
CADC_PD
EAV
04h
Mnemonic
CMDD
ELECTRONICS
General purpose port. This register is useful only if DATAA[2:0] == 7. If DIRA == 0, this bit is
read only and reflects the logic state at PORTA pin. If DIRA == 1, any value written to this bit will
appear at PORTA pin.
Progressive YPbPr Input Mode, ADC sampling clock = 54 MHz
0
1
HS1 and VS pin direction control.
0
1
Video input and clock source select.
0
1
3
Clock select.
0
1
C-ADC’s Power down mode.
0
1
In 8-bit digital CbYCr input mode, this bit selects the sync source.
0
1
bit 7
EAV
Interlaced YPbPr Input Mode.(720x480i)
Progressive YPbPr Input Mode.(720x480p)
HS1 and VS are output.*
HS1 and VS are input.
Video source is analog and connected to the chip’s analog input. Clock is internally
generated.*
Video source is 8-bit digital CbYCr and connected to EXV0 through EXV7 pins.
Video source is 8-bit digitized CVBS and connected to EXV0 through EXV7 pins.
Clock is from internal clock generator. A reference clock at XTALI pin is required.*
Clock is from CK pin. When this is selected, the CK pin automatically becomes an
input.
All ADC’s Power On.
C-ADC’s Power Down, in case of CVBS input modes*.
Horizontal and vertical syncs are from HS1 and VS pins, respectively.*
Syncs are embedded in the 8-bit digital data stream (CCIR 656 compatible).
CADC_PD
bit 6
Control Register D
CKDIR
bit 5
bit 4
INPSL[1:0]
bit 3
SYNDIR
bit 2
MULTIMEDIA VIDEO
PROG
bit 1
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GPPORT
bit 0
7/18/03