FW912 Micron Semiconductor Products, FW912 Datasheet

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FLASH MEMORY FEATURES • Single device supports asynchronous, page, and burst operations • Flexible dual-bank architecture Support for true concurrent operation with zero latency Read bank a during program bank b and vice versa Read bank a during erase bank ...

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... MARKING FW906 FX906 FW905 FX905 FW907 FX907 FW908 FX908 FW909 FX909 FW910 FX910 FW911 FX911 FW912 FX912 2 ADVANCE 4 MEG x 16 MECHANICAL SAMPLE MARKING FY906 FY905 FY907 FY908 FY909 FY910 FY911 FY912 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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PART NUMBERING INFORMATION Micron’s low-power devices are available with sev- eral different combinations of features (see Figure 1). Micron Technology Flash Family 28F = Dual-Supply Flash Density/Organization/Banks 642 = 64Mb (4,096K x 16) bank a = 1/4; bank b = ...

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DQ0–DQ15 Data Input Buffer RST# CE# CSM WE# OE# WSM I/O Logic Address Input A0–A21 Buffer ADV# Address Latch CLK BSM 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ASYNC/PAGE/BURST FLASH MEMORY FUNCTIONAL BLOCK DIAGRAM ...

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Bank b = 48Mb Block Block Size Address Range (K-bytes/ (x16) K-words) 134 64/32 3F8000h–3FFFFFh 133 64/32 3F0000h–3F7FFFh 132 64/32 3E8000h–3EFFFFh 131 64/32 3E0000h–3E7FFFh 130 64/32 3D8000h–3DFFFFh 129 64/32 3D0000h–3D7FFFh 128 64/32 3C8000h–3CFFFFh 127 64/32 3C0000h–3C7FFFh 126 64/32 3B8000h–3BFFFFh 125 ...

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Bank a = 16Mb Block Block Size Address Range (K-bytes/ (x16) K-words) 134 8/4 3FF000h–3FFFFFh 133 8/4 3FE000h–3FEFFFh 132 8/4 3FD000h–3FDFFFh 131 8/4 3FC000h–3FCFFFh 130 8/4 3FB000h–3FBFFFh 129 8/4 3FA000h–3FAFFFh 128 8/4 3F9000h–3F9FFFh 127 8/4 3F8000h–3F8FFFh 126 64/32 3F0000h–3F7FFFh 125 ...

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BALL DESCRIPTIONS 59-BALL FBGA NUMBERS SYMBOL E8, D8, C8, B8, A0–A21 A8, B7, A7, C7, A2, B2, C2, A1, B1, C1, D2, D1, D4, B6, A6, C6, B3 CLK C4 ADV CE# F8 OE# ...

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BALL DESCRIPTIONS (continued) 59-BALL FBGA NUMBERS SYMBOL A4 Supply CC E1 Supply CC G2 Supply SS A3 Supply SS D7 – 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – ...

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COMMAND STATE MACHINE (CSM) Commands are issued to the command state ma- chine (CSM) using standard microprocessor write tim- ings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are ...

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STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE# and reading the resulting status code on I/Os DQ0–DQ7. ...

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CODE DEVICE MODE BUS CYCLE 10h APA 20h Erase Setup 40h Program Setup 50h Clear Status Register 60h Protection Configuration Setup Set Read Configuration Register 70h Read Status Register 90h Read Protection Configuration 98h Read Query B0h Program Suspend Erase ...

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CODE DEVICE MODE BUS CYCLE C0h Program Device Protection Register Lock Device Protection Register D0h Erase Confirm Second Program/Erase/ Check Block Erase Resume FFh Read Array 01h Lock Block Second 03h Read Configuration Second Register Data 2Fh Lock Down Second ...

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During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PRO- GRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its ...

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Command State Machine Transition Table ...

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Command State Machine Transition Table (continued ...

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Command State Machine Transition Table (continued ...

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Command State Machine Transition Table (continued ...

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MODE Read (array, status registers, device identification register, or query) Standby Output Disable Reset Write WSMS ESS 7 6 STATUS BIT # STATUS REGISTER BIT SR7 WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR6 ERASE SUSPEND ...

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PROGRAMMING OPERATIONS There are two CSM commands for programming: PROGRAM SETUP and ACCELERATED PROGRAM- MING ALGORITHM (see Table 3). PROGRAM SETUP COMMAND After the 40h command code is entered on DQ0- DQ7, the WSM takes over and correctly sequences the ...

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ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 8 also possible that an ERASE in any bank can be suspended and a WRITE to ...

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Figure 4 Automated Word Programming Flowchart Start Issue PROGRAM SETUP Command and Word Address Issue Word Address and Word Data Read Status Register Bits NO NO PROGRAM SR7 = 1? SUSPEND? YES Full Status Register 1 Check (optional) Word Program ...

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Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart Start Issue PROGRAM SUSPEND Command Read Status Register Bits NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command NO Finished Reading ? YES Issue PROGRAM RESUME Command PROGRAM ...

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Figure 6 Accelerated Program Algorithm Flowchart Start SR3 = 0? YES Issue the ACCELERATED PROGRAMMING ALGORITHM Command (10h) and Word Address Issue 32 sequences of Word Data SR7 = 1? YES PROGRAM Complete 4 Meg x 16 Async/Page/Burst Flash Memory ...

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Figure 7 BLOCK ERASE Flowchart Start Issue ERASE SETUP Command and Block Address Issue BLOCK ERASE CONFIRM Command and Block Address Read Status Register Bits SUSPEND? YES Full Status Register 1 Check (optional) BLOCK ...

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Figure 8 ERASE SUSPEND/ERASE RESUME Flowchart Start Issue ERASE SUSPEND Command Read Status Register Bits SR7 = 1? YES SR6 = 1? YES READ or PROGRAM? READ Issue READ ARRAY Command READ or NO PROGRAM Complete? YES Issue ERASE RESUME ...

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Figure 9 CHECK BLOCK ERASE Flowchart Start Issue ERASE SETUP Command and Block Address Issue CHECK BLOCK ERASE CONFIRM Command and Block Address NO SR7 = 1? YES NO SR5 = 0? YES BLOCK ERASE Complete 4 Meg x 16 ...

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READ-WHILE-WRITE/ERASE CONCURRENCY It is possible for the device to read from one bank while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a READ CONCURRENCY operation, ...

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BIT # DESCRIPTION 15 Read Mode (RM) 14 Reserved 13–11 Latency Counter (LC) 10 Wait Signal Polarity (WSP) 9 Hold Data Out (HDO) 8 Wait Configuration (WC) 7 Burst Sequence (BS) 6 ...

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LATENCY COUNTER The latency counter provides the number of clocks that must elapse after ADV# is set active before data will be available. This value depends on the input clock frequency. See Table 10 for the specific input clock frequency ...

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BURST SEQUENCE The burst sequence specifies the address order of the data in synchronous burst mode. It can be pro- grammed as either linear or interleaved burst order. Continuous burst length only supports linear burst order. See Table 11 for ...

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BURST WRAP The burst wrap option, RCR3, signals if a four eight-word linear burst access wraps within the burst length or whether it crosses the eight-word boundary. In wrap mode (RCR3 = 0) the four- or eight-word access ...

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WAIT# SIGNAL IN BURST MODE In the continuous burst mode or in the four- or eight- word burst mode with no wrap (RCR3 = 1), the output WAIT# informs the system when data is valid. When WAIT# is asserted during ...

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STATUS REGISTER ERROR CHECKING Using nested locking or program command se- quences during erase suspend can introduce ambigu- ity into status register results. Following protection configuration setup (60h), an invalid command will produce a lock command error (SR4 and SR5 ...

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PROGRAMMING THE CHIP PROTECTION REGISTER The first 64 bits (PR1) of the chip protection register (addresses 81h–84h) are programmed with a unique identifier at the factory. DQ0 of the PR lock register (address 80h) is programmed to a “0” state, ...

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ASYNCHRONOUS PAGE READ MODE After power-up or reset, the device operates in page mode over the whole memory array. The page size can be customized at the factory to four or eight words as required; but if no specification is ...

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ABSOLUTE MAXIMUM RATINGS* Voltage to Any Ball Except V and V CC with Respect to V ....................... -0.5V to +2.45V SS V Voltage (for BLOCK ERASE and PROGRAM PP with Respect ................. -0.5V to +13.5V ...

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AC Input/Output Reference Waveform Input test inputs are driven at V for a logic 1 and Q/2. Input rise and fall times (10% to 90%) < 5ns. CC CAPACITANCE ...

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DC CHARACTERISTICS PARAMETER Input Low Voltage Input High Voltage Output Low Voltage I = 100µA OL Output High Voltage I = -100µ Lockout Voltage PP V During PROGRAM/ERASE Operations PP V Program/Erase Lock Voltage CC Input Leakage ...

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ASYNCHRONOUS READ CYCLE TIMING REQUIREMENTS PARAMETER Address setup to ADV# HIGH CE# LOW to ADV# HIGH READ cycle time Address to output delay CE# LOW to output delay ADV# LOW to output delay ADV# pulse width LOW ADV# pulse width ...

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WRITE CYCLE TIMING REQUIREMENTS PARAMETER HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width ADV# pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH ADV# setup to WE# going ...

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SINGLE ASYNCHRONOUS READ OPERATION V IH A0–A21 ADV WAIT DQ0–DQ15 V OL ...

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ASYNCHRONOUS PAGE MODE READ OPERATION V IH A3–A21 A0– ADV WAIT# V ...

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SINGLE SYNCHRONOUS READ OPERATION V IH CLK AKS AKH V IH A0–A21 VALID ADDRESS VPH IH ADV AADV VKS ...

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SYNCHRONOUS BURST OPERATION V IH CLK AKS AKH V IH A0–A21 VALID ADDRESS VPH IH ADV AADV VKS ...

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SHOWING AN OUTPUT DELAY WITH RCR8 = 0( CLK CLK V IH A0–A21 ADV ...

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TWO-CYCLE PROGRAMMING/ERASE OPERATION V IH A0–A21 ADV DQ0–DQ15 RST ...

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RST OE DQ0–DQ15 V OL READ AND WRITE TIMING PARAMETERS -70 SYMBOL MIN MAX t 1 RWH – 100 t NOTE: 1. For ...

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OFFSET DATA 0 2Ch Manufacturer code 1 B6h Top boot block device code B7h Bottom boot block device code 02 – 0F reserved Reserved 10,11 0051, 0052 “QR” 12 0059 “Y” 13, 14 0003, 0000 Primary OEM command set 15, ...

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OFFSET DATA 37, 38 0020–0000 Top boot block device …..of 8KB 0000–0001 Bottom boot block device …..of 64KB 39, 3A 0050, 0052 “PR” 3B 0049 “I” 3C 0030 Major version number, ASCII 3D 0031 Minor version number, ASCII 3E 00E6 ...

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C 0.80 ±0.075 SEATING PLANE C BALL A8 59X Ø 0.35 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0. 12.00 ± 0.10 2.25 ±0.05 6.00 ±0.05 2.625 ±0.05 NOTE: 1. ...

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REVISION HISTORY Rev. 3, ADVANCE .................................................................................................................................................................... 8/02 • Clarified device specific V Rev. 2, ADVANCE .................................................................................................................................................................... 7/02 • Changed low power consumption voltage from 1.90V to 2.20V • Corrected top boot block device address range for blocks 123 and 125 ...