FW912 Micron Semiconductor Products, FW912 Datasheet - Page 34

• Manufacturer Part Number: FW912
• Description: Flash Memory Technology
• Manufacturer: Micron Semiconductor Products

PROGRAMMING THE CHIP PROTECTION
REGISTER
(addresses 81h–84h) are programmed with a unique
identifier at the factory. DQ0 of the PR lock register
(address 80h) is programmed to a “0” state, locking the
first 64 bits and preventing any further programming.
85h–88h), where the user can program any informa-
tion into this area as long as DQ1 of the PR lock register
remains unprogrammed. After DQ1 of the PR lock reg-
ister is programmed, no further programming is allowed
on PR2. The programming sequence is similar to array
programming except that the PROTECTION REGIS-
TER PROGRAMMING SETUP command (C0h) is issued
instead of an ARRAY PROGRAMMING SETUP com-
mand (40h), followed by the data to be programmed at
addresses 85h–88h.
ther programming), use the above sequence on ad-
dress 80h, with data of FFFDh (DQ1 = 0).
ASYNCHRONOUS READ MODE
read configuration state. To use the device in an
asynchronous-only application, ADV# and CLK must
be tied to V
cess is purely random (
dress, and the CE# signal and the OE# signal must go
LOW. In this case the data is placed on the data bus and
the processor is ready to receive the data.
SYNCHRONOUS BURST READ MODE
rate than is possible with asynchronous read mode.
The rising edge of the clock (CLK) is used to latch the
address with CE# and ADV# LOW (see timing diagram:
Single Synchronous READ Operation). The burst read
configuration is set in the read configuration register,
where frequency, data output, WAIT# signal, burst se-
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
The first 64 bits (PR1) of the chip protection register
The second 64 bits (PR2) is a user area (addresses
To program the PR lock bit for PR2 (to prevent fur-
The asynchronous read mode is the default
Toggling the address lines from A0 to A21, the ac-
The ADV# signal must be toggled to latch the ad-
The burst read mode is used to achieve a faster data
SS
and WAIT# should be floated.
t
AA).
ASYNC/PAGE/BURST FLASH MEMORY
34
quence, clock, and burst length are configured setting
the related bits.
in the following way:
1. In a READ operation there is no bank boundary as
2. If one bank is in program or erase mode and the
3. If a burst access is started in one bank and the bank
Bank a start address
Bank b start address
All blocks in both banks can be burst read.
The BURST READ works across the bank boundary
far as burst access is concerned. If, for example, a
burst starts in bank a, the application can keep clock-
ing until the bank boundary is reached and then
read from bank b. If the application keeps clocking
beyond the last location of bank b, the internal
counter restarts from bank a first address. (See
Figure 14.)
application starts a burst access in that bank, then
the status register data is returned. The internal
address counter is incremented at every clock pulse.
boundary is crossed, and the other bank is in pro-
gram or erase mode, then the status register data is
returned as the first location of the bank. If the ap-
plication keeps clocking, the internal address
counter gets incremented at every clock cycle. If
bank end is crossed, then data from the other bank
is returned as shown in Figure 14.
Bank b end address
Bank a end address
Bank Boundary Wrapping
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(Bottom Boot Example)
Figure 14
0 00000h
0 FFFFFh
0 100000h
1 3FFFFFh
4 MEG x 16
©2002, Micron Technology, Inc.
ADVANCE
Bank a
bank boundary
Bank b