FW912 Micron Semiconductor Products, FW912 Datasheet - Page 19

• Manufacturer Part Number: FW912
• Description: Flash Memory Technology
• Manufacturer: Micron Semiconductor Products

PROGRAMMING OPERATIONS
PROGRAM SETUP and ACCELERATED PROGRAM-
MING ALGORITHM (see Table 3).
PROGRAM SETUP COMMAND
DQ7, the WSM takes over and correctly sequences the
device to complete the PROGRAM operation. The
WRITE operation may be monitored through the sta-
tus register (see the Status Register section). During
this time, the CSM will only respond to a PROGRAM
SUSPEND command until the PROGRAM operation
has been completed, after which time, all commands
to the CSM become valid again. The PROGRAM opera-
tion can be suspended by issuing a PROGRAM SUS-
PEND command (B0h). Once the WSM reaches the
suspend state, it allows the CSM to respond only to
READ ARRAY, READ STATUS REGISTER, READ PRO-
TECTION CONFIGURATION, READ QUERY, PRO-
GRAM SETUP, or PROGRAM RESUME. During the
PROGRAM SUSPEND operation, array data should be
read from an address other than the one being pro-
grammed. To resume the PROGRAM operation, a PRO-
GRAM RESUME command (D0h) must be issued to
cause the CSM to clear the suspend state previously
set (see Figure 4 for programming operation and Figure
5 for program suspend and program resume).
PROGRAM operation.
ACCELERATED PROGRAMMING ALGORITHM
COMMAND
intended for in-system and in-factory use. Its 32
single-word internal buffer enables fast data stream
programming.
ten. Upon activation, the word address and the data
sequences must be provided to the WSM, without poll-
ing SR7. The same starting address must be provided
for each data word. After all 32 sequences are issued,
the status register reports a busy condition. Figure 6
shows the APA flowchart.
FFFFh to complete the data stream. Also, ensure the
starting address is aligned with a 32-word boundary.
interrupted and resumed during programming. When
the APA is active, only a read access in the other bank is
allowed.
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
There are two CSM commands for programming:
After the 40h command code is entered on DQ0-
Taking RP# to V
The accelerated programming algorithm (APA) is
The APA is activated when a 10h command is writ-
If the data stream is shorter than 32 words, use
The APA is fully concurrent. For example, it can be
IL
during programming aborts the
ASYNC/PAGE/BURST FLASH MEMORY
19
optimized set of programming parameters, minimizes
chip programming time when 11.4V ≤ V
the APA and the 32 single-word buffer significantly
improve both the system throughput and the average
programming time when compared with standard pro-
gramming practices. The accelerated programming
functionality executes and verifies the APA without
microprocessor intervention. This relieves the micro-
processor from constantly monitoring the progress of
the programming and erase activity, freeing up valu-
able memory bus bandwidth. This increases the sys-
tem throughput.
ERASE OPERATIONS
bits in an array block to “1s.” After BLOCK ERASE CON-
FIRM is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.
within the address block to logic 1s. Erase is accom-
plished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid ad-
dress within that block. Block erasure is initiated by a
command sequence to the CSM: BLOCK ERASE SETUP
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Figure 7). A two-command erase sequence protects
against accidental erasure of memory contents.
complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are cor-
rectly erased. Monitoring of the ERASE operation is
possible through the status register (see the Status
Register section).
ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows the
CSM to respond only to the READ ARRAY, READ STA-
TUS REGISTER, READ QUERY, READ CHIP PROTEC-
TION CONFIGURATION, PROGRAM SETUP, PRO-
GRAM RESUME, ERASE RESUME, and LOCK SETUP
(see the Block Locking section). During the ERASE SUS-
PEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
For in-factory programming, the APA, along with an
For in-system programming, when 0.9V ≤ V
An ERASE operation must be used to initialize all
Block erasure inside the memory array sets all bits
When the BLOCK ERASE CONFIRM command is
During the execution of an ERASE operation, the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4 MEG x 16
©2002, Micron Technology, Inc.
PP
ADVANCE
≤ 12.6V.
PP
≤ 2.2V,