FW912 Micron Semiconductor Products, FW912 Datasheet - Page 33

• Manufacturer Part Number: FW912
• Description: Flash Memory Technology
• Manufacturer: Micron Semiconductor Products

STATUS REGISTER ERROR CHECKING
quences during erase suspend can introduce ambigu-
ity into status register results.
invalid command will produce a lock command error
(SR4 and SR5 will be set to “1”) in the status register. If
a lock command error occurs during an ERASE SUS-
PEND, SR4 and SR5 will be set to “1” and will remain at
“1” after the ERASE SUSPEND is resumed. When the
ERASE is complete, any possible error during the ERASE
cannot be detected via the status register because of
the previous locking command error.
a program operation error nested within an ERASE
SUSPEND.
CHIP PROTECTION REGISTER
fulfill the security considerations in the system (pre-
venting device substitution).
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit unchange-
able number. The other segment is left blank for cus-
tomers to program as desired. (See Figure 13).
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
Using nested locking or program command se-
Following protection configuration setup (60h), an
A similar situation happens if an error occurs during
A 128-bit chip protection register can be used to
The 128-bit security area is divided into two 64-bit
NOTE: 1. Other locations within the configuration address space are reserved by
ITEM
Manufacturer Code (x16)
Device Code
·
·
Block Lock Configuration
·
·
·
Read Configuration Register
Chip Protection Register Lock
Chip Protection Register 1
Chip Protection Register 2
Top boot configuration
Bottom boot configuration
Block is unlocked
Block is locked
Block is locked down
2. “XX” specifies the block address of lock configuration.
Micron for future use.
Chip Configuration Addressing
Table 13
ASYNC/PAGE/BURST FLASH MEMORY
33
ADDRESS
00000h
00001h
XX002h
00005h
80h
81h–84h
85h–88h
READING THE CHIP PROTECTION REGISTER
identification mode. To enter this mode, load the 90h
command to the bank containing address 00h. Once in
this mode, READ cycles from addresses shown in Table
13 retrieve the specified information. To return to the
read array mode, write the READ ARRAY command
(FFh).
The chip protection register is read in the device
Protection Register Memory Map
88h
85h
84h
81h
80h
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Factory-Programmed
PR Lock
DATA
002Ch
44B6
44B7
Lock
DQ0 = 0
DQ0 = 1
DQ1 = 1
RCR
PR Lock
Factory Data
User Data
User-Programmed
1
Figure 13
4 Words
4 Words
4 MEG x 16
0
©2002, Micron Technology, Inc.
ADVANCE