FM25C040 Fairchild Semiconductor, FM25C040 Datasheet
![no-image](/images/manufacturer_photos/0/2/252/fairchild_semiconductor_sml.jpg)
FM25C040
Available stocks
Related parts for FM25C040
FM25C040 Summary of contents
Page 1
... FM25C040U 4K-Bit SPI™ Interface Serial CMOS EEPROM General Description The FM25C040U (4,096) bit serial interface CMOS EEPROM (Electrically Erasable Programmable Read-Only Memory). This device fully conforms to the SPI 4-wire protocol which uses Chip Select (/CS), Clock (SCK), Data-in (SI) and Data- out (SO) pins to synchronously control data transfer between the SPI microcontroller and the EEPROM ...
Page 2
... Connection Diagram Dual-In-Line Package (N), SO Package (M8), See Package Number N08E (N), M08A (M8), and MTC08 (MT8) Pin Names Ordering Information FM25C040U Rev. B and TSSOP Package (MT8) / /HOLD FM25C040U / SCK Top View /CS Chip Select Input ...
Page 3
... OP example, for 2.1MHz, the period equals 476ns. In this case Note 3: /CS must be brought high for a minimum of t Note 4: This parameter is periodically sampled and not 100% tested. FM25C040U Rev. B ≤ 5.5V Specifications CC Operating Conditions (Note 1) Ambient Operating Temperature -65° ...
Page 4
... In this case Note 7: /CS must be brought high for a minimum of t Note 8: This parameter is periodically sampled and not 100% tested. FM25C040U Rev. B 4.5V Specifications Operating Conditions (Note 5) -65°C to +150°C Ambient Operating Temperature ...
Page 5
... Mode 3 SCK SI Bit 7 Bit 6 Bit 5 Bit 4 High Z SO FIGURE 3. HOLD Timing CS SCK /HOLD SO Output (n+2) SI Input (n+2) FM25C040U Rev CSS t CLH t CLL t DIS t DIH Valid Input Valid Output Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Low state ( / ...
Page 6
... READ 0000A011 WRITE 0000A010 As the FM25C040U requires 9 address bits (4,096 ÷ 512 bytes = 2 Note: the 9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I convention only applies to 4K SPI protocol. In addition to the Instruction register, FM25C040U also contains an 8-bit Status register that can be accessed by RDSR and WRSR instructions. Only the least significant (LSB) 4 bits are defined at present and the most significant (MSB) 4 bits are undefined (don’ ...
Page 7
... SS3 FM25C040U Rev. B SPI Modes 0 and 3 (00 and 11) FM25C040U supports both Mode 0 and Mode 3 of operations. The difference between Mode 0 and Mode 3 is determined by the state of the SCK clock signal when a SPI cycle starts (when /CS is driven low) as well as when the SPI cycle ends (when /CS is driven high) ...
Page 8
... Write to the array is enabled only when /WP pin is held high and the EEPROM is write enabled previously (via WREN instruction). Also, the address of the memory location( programmed must be outside the protected address field selected by the Block Write Protection Level. See Table 4. FM25C040U Rev. B TABLE 4. Block Write Protection Levels Level 0 1 ...
Page 9
... The FM25C040U is also capable byte PAGE WRITE operation. Page write is performed similar to byte write operation described above. During a Page write operation, after the first byte of data, additional bytes ( bytes) can be input, before bringing the /CS pin high to start the programming. After receipt of each byte of data, the EEPROM internally increments the two low order address bits (A1-A0) by one ...
Page 10
... MIN (7.112) 0.300 - 0.320 (7.62 - 8.128) 95° ± 5° 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 FM25C040U Rev. B 0.228 - 0.244 (5.791 - 6.198) Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8° Max, Typ. All leads 0.014 0.016 - 0.050 (0.356) (0.406 - 1.270) ...
Page 11
... Fairchild Semiconductor Fairchild Semiconductor Americas Europe Customer Response Center Tel. 1-888-522-5372 Deutsch English Français Italiano FM25C040U Rev. B 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ Land pattern recommendation See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0118 (0.19 - 0.30) 0°-8° ...