FM25C040 Fairchild Semiconductor, FM25C040 Datasheet - Page 6

• Manufacturer Part Number: FM25C040
• Description: 4K-Bit SPI Interface Serial CMOS EEPROM
• Manufacturer: Fairchild Semiconductor

FM25C040U Rev. B
Pin Description
Chip Select (/CS)
This is an active low input pin to the EEPROM and is generated by
a master that is controlling the EEPROM. A low level on this pin
selects the EEPROM and a high level deselects the EEPROM. All
serial communications with the EEPROM is enabled only when
this pin is held low.
Serial Clock (SCK)
This is an input pin to the EEPROM and is generated by the master
that is controlling the EEPROM. This is a clock signal that
synchronizes the communication between a master and the
EEPROM. All input information (SI) to the EEPROM is latched on
the rising edge of this clock input, while output data (SO) from the
EEPROM is driven after the falling edge of this clock input.
Serial Input (SI)
This is an input pin to the EEPROM and is generated by the master
that is controlling the EEPROM. The master transfers Input
information (Instruction Opcodes, Array addresses and Data)
serially via this pin into the EEPROM. This Input information is
latched on the rising edge of the SCK.
Serial Output (SO)
This is an output pin from the EEPROM and is used to transfer
Output data via this pin to the controlling master. Output data is
serially shifted out on this pin after the falling edge of the SCK.
Hold (/HOLD)
This is an active low input pin to the EEPROM and is generated by
the master that is controlling the EEPROM. When driven low, this
pin suspends any current communication with the EEPROM. The
suspended communication can be resumed by driving this pin
high. This feature eliminates the need to re-transmit the entire
sequence by allowing the master to resume the communication
from where it was left off. This pin should be tied high if this feature
is not used. Refer Hold Function description for additional
details.
Write Protect (/WP)
This is an active low input pin to the EEPROM. This pin allows
enabling and disabling of writes to memory array and status
register of the EEPROM. When this pin is held low, writes to the
memory array and status register are disabled. When this pin is
held high, writes to the memory array and status register are
enabled. Status of this pin does not affect operations other than
array write and status register write. /WP signal going low at any
time will inhibit programming, except when an internal write has
already begun. If an internal write cycle has already begun, /WP
signal going low will have no effect on the write. Refer Table1 for
Write Protection matrix.
Table1. Write Protection Matrix
/WP Pin
High
High
Low
WEN Bit
X
0
1
Status Register
Write Protected
Write Protected
Write Allowed
6
Functional Description
The Serial Peripheral Interface (SPI) of FM25C040U consists of
an 8-bit Instruction register to decode a specific instruction to be
executed. Six different instructions (Opcodes) are incorporated
on FM25C040U for various operations. Table2 lists the instruc-
tions set and the format for proper operation. All Opcodes, Array
addresses and Data are transferred in “MSB first-LSB last”
fashion. Detailed information is provided under individual instruc-
tion descriptions.
TABLE 2. Instruction Set
Note:
the 9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I
convention only applies to 4K SPI protocol.
In addition to the Instruction register, FM25C040U also contains
an 8-bit Status register that can be accessed by RDSR and WRSR
instructions. Only the least significant (LSB) 4 bits are defined at
present and the most significant (MSB) 4 bits are undefined (don’t
care). The LSB 4 bits define Block Write Protection levels (BP1and
BP0), Write-enable status (WEN) and Busy/Rdy status (/RDY) of
the EEPROM. Table 3 illustrates the format:
TABLE 3. Status Register Format
Refer RDSR and WRSR instruction descriptions for additional
information on Status register operations.
Instruction Instruction
Bit
X
7
Name
WRITE
WREN
WRSR
RDSR
READ
WRDI
Protected Blocks
As the FM25C040U requires 9 address bits (4,096 ÷ 8 = 512 bytes = 2
(by BP1-BP0)
Write Protected
Write Protected
Write Protected
Bit
6
X
Opcode
0000A011
0000A010
00000110
00000100
00000101
00000001
Bit
X
5
Bit
X
4
Write Enabled
Write Disabled
Read Status Register
Write Status Register
Read Data from Memory
Array
Write Data to Memory Array
BP1
Bit
3
Unprotected Blocks
Operation
Write Protected
Write Protected
Write Allowed
BP0
Bit
2
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WEN
Bit
1
3
RDY
. This
Bit
0
9
),