S1D13742 Epson, S1D13742 Datasheet - Page 107

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Epson Research and Development
Vancouver Design Center
19.1.2 S1D13742 Register Settings for 352x416 TFT Panel
Hardware Functional Specification
Issue Date: 2007/09/18
REG[04h] bit 7
REG[0Ch]
REG[1Ch]
REG[3Ch]
REG[56h]
REG[04h]
REG[06h]
REG[08h]
REG[0Ah]
REG[0Eh]
REG[12h]
REG[14h]
REG[16h]
REG[18h]
REG[1Ah]
REG[1Eh]
REG[20h]
REG[22h]
REG[24h]
REG[26h]
REG[28h]
REG[2Ah]
REG[56h]
REG[38h]
REG[3Ah]
REG[3Eh]
Register
All
Note
Note
Table 19-2: Example Register Settings for 352x416 TFT Panel
The registers listed below are only those associated with panel specific timing issues All
other registers are not shown here.
When a window is setup for YUV data, the data must always alternate between odd and
even lines, starting with an odd line.
default
Value
2Ch
2Dh
F8h
28h
2Fh
5Ah
A0h
06h
14h
80h
01h
00h
00h
00h
02h
12h
80h
00h
19h
01h
02h
01h
00h
00h
0h
—
Revision 6.01 - EPSON CONFIDENTIAL
Come out of reset - all registers set to default values
enter sleep mode (or use PWRSVE pin)
set PLL M-Divider.
CLKI = 19.2MHz,
PLL input clock = CLKI/19 = 1.01MHz.
LL = 48, resulting SYSCLK = LL x PLL input clock = 48MHz
set PCLK divide, PCLK = 12.1MHz
set SYSCLK source = PLL
no panel data swap, 18-bit panel
HDP = 352 pixels
HNDP = 90 pixels
VDP = 416 lines
VNDP = 6 lines
HS Pulse Width = 20 pixels
HS Start Position = 45 pixels
VS Width = 2 lines
VS Start Position (VFP) = 1 line
PCLK Polarity: data output on falling edge
set memory to 16 bpp,
set input data mode to RGB 5:6:5
disable sleep mode
wait for PLL to lock - poll REG[04h] bit 7
Window X Start Position = 0
Window Y Start Position = 0
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X63A-A-001-06
S1D13742
Page 107
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