S1D13742 Epson, S1D13742 Datasheet - Page 43

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Epson Research and Development
Vancouver Design Center
8.4 Setting SYSCLK and PCLK
Hardware Functional Specification
Issue Date: 2007/09/18
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6
SysClk/7
The period of the system clock, T
range:
14.94ns < T
where T
For example, if the minimum back-to-back cycle time of the Intel 80 Interface is 5 x 9.5 =
47.5ns, then:
14.94ns < T
Therefore,
44.26MHz < f
Care should be taken when setting T
can be achieved. PCLK is an integer divided version of SYSCLK. The following graph
shows the suggested setting for SYSCLK for a given value of PCLK for T
SysClk/6
8
Figure 8-3: Setting of SYSCLK For a Desired PCLK
BBC
SysClk/5
10
SYSCLK
SYSCLK
is the minimum back-to-back cycle time of the Intel 80 Interface.
SYSCLK
Revision 6.01 - EPSON CONFIDENTIAL
12
< (T
< 22.594ns
< 66.95MHz
SysClk/4
BBC
14
PCLK Frequency (MHz)
- 0.914) x 0.485 ns
www.DataSheet.co.kr
SYSCLK
16
SYSCLK
, must be set such that it falls within the following
18
so that the desired PCLK frequency, f
SysClk/3
20
22
24
SysClk/2
BBC
26
X63A-A-001-06
= 47.5ns.
S1D13742
PCLK
Page 43
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