S1D13742 Epson, S1D13742 Datasheet - Page 28

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Page 28
1
S1D13742
X63A-A-001-06
Refer to Section 8.4, “Setting SYSCLK and PCLK” on page 43.
Symbol
t
t
t
PDuty
f
PJref
PStal
PLL
Jitter (ns)
PLL output clock frequency
PLL output clock period jitter
PLL output clock duty cycle
PLL output stable time
The PLL frequency will ramp between the OFF state and the programmed frequency.
To guarantee the lowest possible clock jitter, 10ms is required for stabilization.
Note: PLL minimum frequency = 44.26MHz
MHz
Reference Clock
(Based on Intel 80 cycle length. Refer to Section 8.4 for more information)
PLL maximum frequency = 66.95MHz
PLL Enable
Lock in time
10 ms
Parameter
Table 7-2: PLL Clock Requirements
Revision 6.01 - EPSON CONFIDENTIAL
Figure 7-2: PLL Start-Up Time
Lock In Time
10 ms
Time (ms)
www.DataSheet.co.kr
PLL Stable
PLL xxMHz Output (xx = 44.26~66.95MHz)
44.26
Min
40
⎯
-3
1
Epson Research and Development
Hardware Functional Specification
66.95
Max
60
10
3
Vancouver Design Center
Issue Date: 2007/09/18
Units
MHz
ms
%
%
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