S1D13742 Epson, S1D13742 Datasheet - Page 49

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Epson Research and Development
Vancouver Design Center
bits 6-0
Hardware Functional Specification
Issue Date: 2007/09/18
REG[0Eh] PLL Setting Register 4
Default = 00h
REG[10h]
Default = 00h
n/a
7
7
Target Frequency
(MHz)
53
60
53
60
6
6
•
L-Counter bits [6:0]
These bits are used to configure the PLL Output (in MHz) and must be set according to the
following formula.
Where:
Please refer to Section 8.4, “Setting SYSCLK and PCLK” on page 43 for restrictions on
PLL Output frequencies.
Writes to this register have no effect on hardware. During Auto Increment, a dummy write
needs to be performed to this register.
PLL Output = (L-Counter +1) x PLLCLK
PLL Output is the desired PLL output frequency (in MHz).
L-Counter is the value of this register (in decimal).
PLLCLK is the internal input clock to the PLL (in MHz).
5
5
LL
53
60
53
60
•
Revision 6.01 - EPSON CONFIDENTIAL
Input Clock
= LL x PLLCLK
Table 9-3 PLL Setting Example
(MHz)
CLKI
19.2
19.2
12
12
4
4
•
n/a
www.DataSheet.co.kr
L-Counter bits 6-0
M-Divider
REG[04]
bits 5-0
0Bh
0Bh
12h
12h
3
3
•
M-Divide
Ratio
12:1
12:1
19:1
19:1
•
2
2
PLLCLK
1.0105
1.0105
(MHz)
1.0
1.0
•
1
1
POUT (MHz)
Read/Write
Read/Write
X63A-A-001-06
53.53
60.63
53
60
S1D13742
•
0
0
Page 49
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