S1D13742 Epson, S1D13742 Datasheet - Page 115

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Epson Research and Development
Vancouver Design Center
19.3.1 Panel Timing for 352x416 Panel
1. Ts
19.3.2 Panel Timing for 800x480 Panel
1. Ts
Hardware Functional Specification
Issue Date: 2007/09/18
Symbol
Symbol
t10
t11
t12
t13
t14
t15
t16
t10
t11
t12
t13
t14
t15
t16
t1
t2
t3
t4
t5
t6
t7
t8
t9
t1
t2
t3
t4
t5
t6
t7
t8
t9
= pixel clock period = 83.3 ns (12MHz PCLK)
= pixel clock period = 50.84 (19.67 PCLK)
VS cycle time
VS pulse width low
VS falling edge to HS falling edge phase difference
HS cycle time
HS pulse width low
HS Falling edge to DE active
DE pulse width
DE falling edge to HS falling edge
PCLK period
PCLK pulse width low
PCLK pulse width high
HS setup to PCLK falling edge
DE to PCLK rising edge setup time
DE hold from PCLK rising edge
Data setup to PCLK rising edge
Data hold from PCLK rising edge
VS cycle time
VS pulse width low
VS falling edge to HS falling edge phase difference
HS cycle time
HS pulse width low
HS Falling edge to DE active
DE pulse width
DE falling edge to HS falling edge
PCLK period
PCLK pulse width low
PCLK pulse width high
HS setup to PCLK falling edge
DE to PCLK rising edge setup time
DE hold from PCLK rising edge
Data setup to PCLK rising edge
Data hold from PCLK rising edge
Table 19-6: 18/36-Bit TFT A.C. Timing (352x416 Panel Timing)
Table 19-3
18/36-Bit TFT A.C. Timing (800x480 Panel Timings)
Parameter
Parameter
Revision 6.01 - EPSON CONFIDENTIAL
www.DataSheet.co.kr
50.84
25.42
25.42
25.42
25.42
25.42
25.42
25.42
83.3
41.7
41.7
41.7
41.7
41.7
41.7
41.7
Min
Min
0
0
15.54
73.67
36.83
1.67
3.75
29.3
3.75
Typ
20.34
41.68
40.67
50.84
83.4
1.02
—
—
—
—
—
—
—
—
—
Typ
966
—
—
—
—
—
—
—
—
—
36.75
Max
41.63
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Units
ms
us
us
us
us
us
us
us
ns
ns
ns
ns
ns
ns
ns
ns
ms
us
us
us
us
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
X63A-A-001-06
S1D13742
Page 115
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