S1D13742 Epson, S1D13742 Datasheet - Page 51

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Epson Research and Development
Vancouver Design Center
bit 0
Hardware Functional Specification
Issue Date: 2007/09/18
Note
SYSCLK Source Select
This bit selects the system clock (SYSCLK) source for the controller.
When this bit = 0, the SYSCLK source is the external CLKI input.
When this bit = 1, the SYSCLK source is the internal PLL.
If the PLL is selected as the SYSCLK source (bit 0 = 1), the PLL must be configured using
REG[06h], REG[08h], REG[0Ah], REG[0Ch], REG[0Eh] and REG[10h] before setting
this bit.
To use PLL as system clock source (SYSCLK), Sleep Mode needs to be first enabled,
REG[56h] bit 1 = 1. Once in Sleep Mode, REG[04h] and REG[0Eh] can be changed to
set the desired PLL frequency. Once REG[04h] and REG[0Eh] have been set,
REG[12h] bit 0 can be set to 1b to select PLL as the system clock source. The PLL out-
put will only be active after exiting the Sleep Mode (REG[56h] bit 1 = 0). The PLL out-
put will become stable after 10msec. The display memory or the Gamma Correction
Table must not be accessed before this time. REG[04h] bit 7, the PLL Lock Bit, can be
used to determine if the PLL output is stable.
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S1D13742
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