P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 10

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
6
DBE
LATEABT
LOCK
MCLK
nBW
nCPI
nFIQ
nIRQ
nMREQ
nOPC
Name
Type
OS8
OS8
O4
O4
O4
I
I
I
I
I
Data bus enable. When DBE is LOW the write data register output drivers are disabled.
When DBE goes HIGH these output drivers are enabled. DBE facilitates data bus sharing for
DMA and so on.
Late abort. This signal controls the action of the processor on an abort exception. When it is
HIGH (Late abort) the modified base register of an aborted LDR or STR instruction is written
back. When it is LOW (Early abort) the modified base register is not written back. LATEABT
must not be changed during the execution of a data access instruction where abort is active.
It is recommended that the Late abort scheme be used where possible as this scheme will be
used in future ARM processors.
Locked operation. When LOCK is HIGH, the processor is performing a ÒlockedÓ memory
access, and the memory controller must wait until LOCK goes LOW before allowing another
device to access the memory. LOCK changes while MCLK is HIGH, and remains HIGH for
the duration of the locked memory accesses. It is active only during the data swap (SWP)
instruction.
Memory clock input. This clock times all ARM60 memory accesses and internal operations.
The clock has two distinct phases - phase 1 in which MCLK is LOW and phase 2 in which
MCLK (and nWAIT ) is HIGH. The clock may be stretched indefinitely in either phase to
allow access to slow peripherals or memory. Alternatively, the nWAIT input may be used
with a free running MCLK to achieve the same effect.
Not byte/word. This is an output signal used by the processor to indicate to the external
memory system when a data transfer of a byte length is required. The signal is HIGH for
word transfers and LOW for byte transfers and is valid for both read and write cycles. The
signal will become valid during phase 2 of the cycle before the one in which the transfer will
take place. It will remain stable throughout phase 1 of the transfer cycle.
Not Coprocessor instruction. When ARM60 executes a coprocessor instruction, it will take
this output LOW and wait for a response from the coprocessor. The action taken will depend
on this response, which the coprocessor signals on the CPA and CPB inputs.
Not fast interrupt request. This is an asynchronous interrupt request to the processor which
causes it to be interrupted if taken LOW when the appropriate enable in the processor is
active. The signal is level sensitive and must be held LOW until a suitable response is
received from the processor.
Not interrupt request. As nFIQ , but with lower priority. May be taken LOW asynchronously
to interrupt the processor when the appropriate enable is active.
Not memory request. This signal, when LOW, indicates that the processor requires memory
access during the following cycle. The signal becomes valid during phase 1, remaining valid
through phase 2 of the cycle preceding that to which it refers.
Not op-code fetch. When LOW this signal indicates that the processor is fetching an
instruction from memory; when HIGH, data (if present) is being transferred. The signal
becomes valid during phase 2 of the previous cycle, remaining valid through phase 1 of the
referenced cycle.
Table 1: Signal Description
Description