P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 25

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

4.3 Branch and Branch with link (B, BL)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter. The instruction encoding is shown in Figure 7: Branch Instructions .
Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended
to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch
offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the
current instruction.
Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously
loaded into a register. In this case the PC should be manually saved in R14 if a Branch with Link type
operation is required.
4.3.1 The link bit
Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value
written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following
the branch and link instruction. Note that the CPSR is not saved with the PC.
To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or
LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn.
4.3.2 Instruction Cycle Times
Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are as defined in
section 5.1 Cycle types on page 65.
4.3.3 Assembler syntax
B{L}{cond} <expression>
{L} is used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the
instruction.
{cond} is a two-char mnemonic as shown in Figure 6: Condition Codes (EQ, NE, VS etc). If absent then AL
(ALways) will be used.
31
Cond
28 27
101
25 24 23
L
Link bit
Condition field
0 = Branch
1 = Branch with Link
Figure 7: Branch Instructions
offset
Instruction Set - B, BL
0
21