P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 55

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

4.10.5 Examples
The above examples assume that suitable supervisor code exists, for instance:
Supervisor
; SWI has routine required in bits 8-23 and data (if any) in bits 0-7.
; Assumes R13_svc points to a suitable stack
SWI
SWI
SWINE
0x08 B Supervisor
EntryTable
Zero
ReadC
WriteI
STMFD
LDR
BIC
MOV
ADR
LDR
WriteIRtn
LDMFD
. . .
. . . . . .
ReadC
WriteI+”k”
0
DCD ZeroRtn
DCD ReadCRtn
DCD WriteIRtn
EQU
EQU
EQU
R13,{R0-R2,R14}
R0,[R14,#-4]
R0,R0,#0xFF000000
R1,R0,LSR#8
R2,EntryTable
R15,[R2,R1,LSL#2]
R13,{R0-R2,R15}^
0
256
512
; get next character from read stream
; output a “k” to the write stream
; conditionally call supervisor
; with 0 in comment field
; SWI entry point
; addresses of supervisor routines
; save work registers and return address
; get SWI instruction
; clear top 8 bits
; get routine offset
; get start address of entry table
; branch to appropriate routine
; enter with character in R0 bits 0-7
; restore workspace and return
; restoring processor mode and flags
Instruction Set - SWI
51