P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 60
P60ARM-B
Manufacturer Part Number
P60ARM-B
Description
32-bit RISC microprocessor
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.P60ARM-B.pdf
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P60ARM-B
LDC - load from memory to coprocessor
STC - store from coprocessor to memory
{L} - when present perform long transfer (N=1), otherwise perform short transfer (N=0)
{cond} - two character condition mnemonic, see Figure 6: Condition Codes
p# - the unique number of the required coprocessor
cd is an expression evaluating to a valid coprocessor register number that is placed in the CRd field
<Address> can be:
(i)
(ii)
(iii)
Rn is an expression evaluating to a valid ARM60 register number. Note, if Rn is R15 then the assembler will
subtract 8 from the offset value to allow for ARM60 pipelining.
{!} write back the base register (set the W bit) if ! is present
4.12.8 Examples
Note that though the address offset is expressed in bytes, the instruction offset field is in words. The
assembler will adjust the offset appropriately.
56
An expression which generates an address:
<expression>
The assembler will attempt to generate an instruction using the PC as a base and a corrected
immediate offset to address the location given by evaluating the expression. This will be a PC
relative, pre-indexed address. If the address is out of range, an error will be generated.
A pre-indexed addressing specification:
[Rn] offset of zero
[Rn,<#expression>]{!} offset of <expression> bytes
A post-indexed addressing specification:
[Rn],<#expression> offset of <expression> bytes
LDC
STCEQL
p1,c2,table
p2,c3,[R5,#24]!
; load c2 of coproc 1 from address table,
; using a PC relative address.
; conditionally store c3 of coproc 2 into
; an address 24 bytes up from R5, write this
; address back to R5, and use long transfer
; option (probably to store multiple words)
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