FAN5018B Fairchild Semiconductor, FAN5018B Datasheet - Page 2

• Manufacturer Part Number: FAN5018B
• Description: 6-Bit VID Controller 2-4 Phase VR10.X Controller
• Manufacturer: Fairchild Semiconductor

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FAN5018B
Pin Assignments
Pin Definitions
2
Pin Number
1–5
10
11
12
13
14
15
6
7
8
9
RAMPADJ
Pin Name
VID5/SEL
VID [4:0]
PWRGD
FBRTN
DELAY
COMP
ILIMIT
EN
RT
FB
Pin Function Description
VID inputs. Determines the output voltage via the internal DAC. These inputs
comply to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups (1.25V for VRM10 and 2.5V for VRM9) so leaving them open
results in logic high. Leaving VID[4:0] open results in a "No CPU" condition
disabling the PWM outputs.
VID5 Input/DAC Select. Dual function pin that is either the 12.5mV DAC LSB for
VRM10 or selects the VRM9 DAC codes when forced higher than Vtblsel(VRM9)
voltage. The truth table is as follows:
V
V
V
Feedback Return. Error Amp and DAC reference point.
Feedback Input. Inverting input for Error Amp this pin is used for external
compensation. This pin can also be used to introduce DC offset voltage to the
output.
Error Amp output. This pin is used for external compensation.
Power Good output. This is an open-drain output that asserts when the output
voltage is within the specified tolerance. It is expected to be pulled up to an external
voltage rail.
Enable. Logic signal that enables the controller when logic high.
Soft-start and Current Limit Delay. An external resistor and capacitor sets the
softstart ramp rate and the over-current latch off delay.
Switching Frequency Adjust. This pin adjusts the output PWM switching
frequency via an external resistor.
PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of
the internal PWM ramp.
Current Limit Adjust. An external resistor sets the current limit threshold for the
regulator circuit. This pin is internally pulled low when EN is low or the UVLO circuit
is active. It is also used to enable the drivers.
VID5/SEL
ViD5/SEL
ViD5/SEL
RAMPADJ
VID5/SEL
PWRGD
FBRTN
DELAY
COMP
VID4
VID3
VID2
VID1
VID0
EN
FB
RT
< Vtblsel(VRM10); VRM10 DAC table is selected (See Table 2) and
pin is used as VID5 input.
held > Vtblsel(VRM9); VRM9 DAC table is selected (See Table 3)
10
11
12
13
14
1
2
3
4
5
6
7
8
9
FAN5018B
TSSOP-28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT
PRODUCT SPECIFICATION
REV. 1.0.0 Jul/15/05