FAN5018B Fairchild Semiconductor, FAN5018B Datasheet - Page 24

• Manufacturer Part Number: FAN5018B
• Description: 6-Bit VID Controller 2-4 Phase VR10.X Controller
• Manufacturer: Fairchild Semiconductor

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FAN5018B
This limit can be adjusted by changing the ramp voltage V
Do not set the per-phase limit lower than the average per-
phase current (I
There is also a per phase initial duty cycle limit determined
by:
For this example, the maximum duty cycle is found to be
0.2696.
Feedback Loop Compensation Design
Optimized compensation of the FAN5018B allows the best
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an
output impedance that is entirely resistive over the widest
possible frequency range, including DC, and equal to the
droop resistance (R
the output voltage will droop in proportion with the load
current at any load current slew rate; this ensures the optimal
positioning and allows the minimization of the output
decoupling.
With the multimode feedback structure of the FAN5018B,
the feedback compensation should be set to make the con-
verter’s output impedance work in conjunction with the out-
put decoupling to meet this goal. The output inductor and
decoupling capacitors (output filter) create several poles and
zeros that require compensation.
A type-III compensator on the voltage feedback is adequate
for proper compensation of the output filter. The expressions
given in Equations 25–29 are intended to yield an optimal
starting point for the design; some adjustments may be nec-
essary to account for PCB and component parasitic effects
(see the Tuning Procedure for the FAN5018B section).
The first step is to compute the time constants for all of the
poles and zeros in the system:
24
T
T
T
R
D
R
E
A
B
A
E
MAX
=
=
=
=
=
n
. 6
(
C
3
×
R
56
=
×
R
X
X
O
1
mF
D
×
+
+
3 .
(
R
×
A
m
R
×
D
'
V
−
O
Ω
(
×
1
R
COMP
−
R
3 .
O
+
LIM/n
DS
m
R
)
5
×
+
Ω
'
(
×
)
C
MAX
O
V
R
+
−
. 5
).
). With the resistive output impedance,
L
X
V
RT
0
×
L
R
VID
95
)
6 .
V
X
O
−
RT
m
m
×
V
Ω
Ω
+
BIAS
R
)
2
+
O
+
R
×
n
1
−
375
L
1
X
×
6 .
3 .
×
R
C
(
m
m
1
X
'
pH
Ω
−
Ω
×
1
n
R
5 .
×
×
×
O
V
. 0
1
D
×
3 .
V
)
974
VID
×
m
V
1
Ω
RT
0 .
V
−
m
+
0
Ω
6 .
2
m
×
Ω
3
650
×
=
. 6
. 4
(24)
nH
56
79
R
mF
(25)
(26)
μ
(27)
×
.
s
(
1
×
−
1
. 0
where, for the FAN5018B, R' is the PCB resistance from the
bulk capacitors to the ceramics and where R
mately the total low-side MOSFET ON resistance per phase
at 25ºC. For this example, A
approximately 0.6m
L
The compensation values can then be solved using the fol-
lowing equations:
3 .
C
T
T
T
T
T
C
C
C
R
375
X
C
m
B
C
D
D
A
A
A
B
FB
=
is 375pH for the eight Al-Poly capacitors.
Ω
=
=
=
=
=
=
=
=
)
=
(
V
. 0
. 6
C
3
×
×
1
C
T
n
T
R
55
RT
974
0 .
C
T
1
56
×
R
. 0
X
A
B
R
B
×
5 .
D
1
m
3 .
A
×
974
×
E
=
mF
R
=
3 .
V
V
Ω
m
=
⎛
⎜ ⎜
⎝
V
(
×
C
O
. 6 μ
253
m
. 1
R
. 1
L
VID
×
Ω
R
V
+
×
27
X
O
86
Ω
33
500
1
×
97
−
. 6
⎛
⎜
⎝
B
T
0
5 .
×
×
650
−
(
×
pF
1 .
56
=
1
×
k
6 .
A
A
μ
V
. 1
2
C
Ω
R
R
3 .
s
k
D
ns
. 4
s
55
m
mF
×
33
×
Z
Ω
E
nH
'
m
×
=
)
79
Ω
=
×
55
3 .
f
+
Ω
Ω
k
R
27
=
SW
. 1
R
−
×
Ω
μ
m
C
DS
−
3 .
18
−
(assuming a 4-layer motherboard) and
48
1 .
1
O
s
2
220
Z
Ω
m
5
2
3 .
⎞
⎟ ⎟
⎠
0
k
=
×
5 .
nF
×
Ω
×
6 .
Ω
m
. 6
R
253
μ
228
pF
m
Ω
O
F
95
Ω
D
)
×
×
kHz
pF
m
)
is 5, V
(
+
. 6
Ω
1
3 .
220
56
⎞
⎟
⎠
m
PRODUCT SPECIFICATION
=
mF
Ω
μ
. 6
RT
F
)
86
2
=
×
equals 0.974V, R' is
REV. 1.0.0 Jul/15/05
. 1
μ
1
s
3 .
97
m
DS
μ
Ω
s
is approxi-
=
500
ns
(28)
(29)
(30)
(31)
(32)
(33)