nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 24

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
4.2.3.3 ShockBurst™ Receive:
4.2.3.3.1 CPU interface pins: CE, DR1, CLK1 and DATA (one RX channel receive)
In ShockBurst™ mode the nRF24E1 can facilitate simultaneous reception of two
parallel independent frequency channels at the maximum data rate.
This means:
The DuoCeiver™ technology provides 2 separate dedicated data channels for RX and
replaces the need for two, stand alone receiver systems.
Figure 4-6 Simultaneous 2 channel receive on nRF24E1
There is one absolute requirement for using the second data channel. For the nRF24E1
to be able to receive at the second data channel the frequency channel must be 8MHz
higher than the frequency of data channel 1. The nRF2401 subsystem must be
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
1. Correct address and size of payload of incoming RF packages are set when
2. To activate RX, set CE high.
3. After 200 s settling, nRF2401 subsystem is monitoring the air for
4. When a valid package has been received (correct address and CRC found),
5. nRF2401 subsystem then notifies (interrupts) the CPU by setting the DR1
6. CPU may set the CE low to disable the RF front end (low current mode).
7. The CPU will clock out just the payload data at a suitable rate (ex. 10
8. When all payload data is retrieved nRF2401 subsystem sets DR1 low
nRF2401 subsystem is configured to ShockBurst™ RX.
incoming communication.
nRF2401 subsystem removes the preamble, address and CRC bits.
pin high.
kbps).
again, and is ready for new incoming data package if CE is kept high
during data download. If the CE was set low, a new start up sequence can
begin, see Figure 4-14.
nRF24E1 can receive data from two 1 Mbps transmitters (ex: nRF24E1,
nRF2401 or nRF2402) 8 MHz (8 frequency channels) apart through one
antenna interface.
The output from the two data channels is fed to two separate sets of
interface pins.
Data channel 1: CLK1, DATA, and DR1
Data channel 2: CLK2, DOUT2, and DR2
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July 2003