nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 49

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
The internal timers and serial port generate interrupts by setting their respective
SFR interrupt flag bits. The CPU samples external interrupts once per
instruction cycle, at the rising edge of CPU_clk at the end of cycle C4.
The INT0_N and INT1_N signals are both active low and can be programmed
through the IT0 and IT1 bits in the TCON SFR to be either edge-sensitive or
level-sensitive. For example, when IT0 = 0, INT0_N is level-sensitive and the
CPU sets the IE0 flag when the INT0_N pin is sampled low. When IT0 = 1,
INT0_N is edge-sensitive and the CPU sets the IE0 flag when the INT0_N pin
is sampled high then low on consecutive samples. To ensure that edge-sensitive
interrupts are detected, the corresponding ports should be held high for four
clock cycles and then low for four clock cycles. Level-sensitive interrupts are
not latched and must remain active until serviced.
Interrupt response time depends on the current state of the CPU. The fastest
response time is five instruction cycles: one to detect the interrupt, and four to
perform the LCALL to the ISR.The maximum latency (thirteen instruction
cycles) occurs when the CPU is currently executing an RETI instruction
followed by a MUL or DIV instruction. The thirteen instruction cycles in this
case are: one to detect the interrupt, three to complete the RETI, five to execute
the DIV or MUL, and four to execute the LCALL to the ISR.
For the maximum latency case, the response time is 13 x 4 =52clock cycles.
nRF24E1 may be set into Power Down state by writing 0x2 or 0x3 to SFR 0xB6,
register CK_CTRL. The CPU will then perform a controlled shutdown of clock and
power regulator. The system can only be restarted from an external interrupt, an RTC
wakeup or a Watchdog reset. In this case the CPU cannot respond until the clock and
power regulator have restarted, which may take 3 to 4 LP_OSC cycles. This delay
may vary from 0.6ms to 4 ms depending on processing, temperature and supply
voltage. In the same way, the shutdown also takes from 2 to 3 LP_OSC cycles, which
will be in the range of 0.4 - 3ms.
The nRF24E1 interrupt structure provides a way to perform single-step
program execution. When exiting an ISR with an RETI instruction, the CPU
will always execute at least one instruction of the task program. Therefore, once
an ISR is entered, it cannot be re-entered until at least one program instruction
is executed. To perform single-step execution, program one of the external
interrupts (for example, INT0_N) to be level-sensitive and write an ISR for that
interrupt that terminates as follows:
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
JNB TCON.1,$ ;
JB TCON.1,$ ;
RETI ;
return for ISR
wait for high on INT0_N
wait for low on INT0_N
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July 2003