nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 44

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
nRF24E1 supports the following interrupt sources:
Interrupt signal
INT0_N
TF0
INT1_N
TF1
TF2 or EXF2
TI or RI
int2
int3
int4
int5
wdti
Table 7-1 : nRF24E1 interrupt sources
The following SFRs are associated with interrupt control:
- IE – SFR 0xA8 (
- IP – SFR 0xB8 (
- EXIF – SFR 0x91 (
- EICON – SFR 0xD8 (
- EIE – SFR 0xE8 (
- EIP – SFR 0xF8 (
The IE and IP SFRs provide interrupt enable and priority control for the
standard interrupt unit, as with industry standard 8051. The EXIF, EICON, EIE,
and EIP registers provide flags, enable control, and priority control for the
extended interrupt unit.
Table 7-2
Bit
IE.7
IE.6
IE.5
IE.4
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
explains the bit functions of the IE register.
Function
EA - Global interrupt enable. Controls masking of all interrupts. EA = 0
disables all interrupts (EA overrides individual interrupt enable bits).
When EA = 1, each interrupt is enabled or masked by its individual
enable bit.
Reserved. Read as 0.
ET2 - Enable Timer 2 interrupt. ET2 = 0 disables Timer 2 interrupt
(TF2). ET2 = 1 enables interrupts generated by the TF2 or EXF2 flag.
ES - Enable Serial Port interrupt. ES = 0 disables Serial Port interrupts
(TI and RI). ES = 1 enables interrupts generated by the TI or RI flag.
Description
External interrupt, active low, configurable as edge-sensitive or
level-sensitive, at Port P0.3
Timer 0 interrupt
External interrupt, active low, configurable as edge-sensitive or
level-sensitive, at Port P0.4
Timer 1 interrupt
Timer 2 interrupt
Receive/transmit interrupt from Serial Port
Internal ADC_EOC (end of AD conversion) interrupt
Internal SPI_READY interrupt
Internal RADIO.DR1 interrupt (a packet is ready from receiver 1)
Internal RADIO.DR2 interrupt (a packet is ready from receiver 2)
Internal RTC wakeup timer interrupt
Table 7-3
Table 7-2
Table 7-7
Table 7-6
Table 7-4
Table 7-5
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July 2003