nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 68

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
Table 10-11 lists the functions of the bits in the PSW register.
Bit
PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0
Table 10-11 : PSW Register – SFR 0xD0
The table below lists the SFR registers that are unique to nRF24E1 (not part of
standard 8051 register map) The registers P0, P1 and RADIO use the addresses for the
ports P0, P1 and P2 in a standard 8051. Whereas the functionality of these ports is
similar to that of the corresponding ports in standard 8051, it is not identical.
4
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
This bit addressable register differs in usage from “standard 8051”
90*
Only 3 lower bits are meaningful in P1 and corresponding P1_DIR and P1_ALT
80
94
95
96
97
R/W
R/W
R/W
R/W
R/W
R/W
8(3)
8(3)
8(3)
8
8
8
F0 - User flag 0. Bit-addressable, general purpose flag for software control.
RS0 - Register bank select bit 0, decoded as:
F1 - User flag 1. Bit-addressable, general purpose flag for software control.
P - Parity flag. Set to 1 when modulo-2 sum of 8 bits in accumulator is 1 (odd parity);
Function
CY - Carry flag. Set to 1 when last arithmetic operation resulted in a carry (during
addition) or borrow (during subtraction); otherwise cleared to 0 by all arithmetic
operations.
AC - Auxiliary carry flag. Set to 1 when last arithmetic operation resulted in a carry into
(during addition) or borrow from (during subtraction) the high-order nibble; otherwise
cleared to 0 by all arithmetic operations.
RS1 - Register bank select bit 1. Used with RS0 to select a register blank in internal
RAM.
OV - Overflow flag. Set to 1 when last arithmetic operation resulted in a carry (addition),
borrow (subtraction), or overflow (multiply or divide); otherwise cleared to 0 by all
arithmetic operations.
cleared to 0 on even parity.
RS1 RS0 Bank selected
0
0
1
1
0
1
0
1
FF
FF
FF
FF
00
00
Register bank 0, addresses 0x00-0x07
Register bank 1, addresses 0x08-0x0F
Register bank 2, addresses 0x10-0x17
Register bank 3, addresses 0x18-0x1F
P0
P1
P0_DIR
P0_ALT
P1_DIR
P1_ALT
4
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Port 0, pins DIO9 to DIO2
Port 1, pins DIN0, DI1, DI0
Direction of each GPIO bit of port 0
Select alternate functions for each pin of port 0
Direction for each GPIO bit of port 1
Select alternate functions for each pin of port 1
July 2003