nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 48

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nRF24E1

Manufacturer Part Number
nRF24E1
Description
2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
Manufacturer
Nordic VLSI
Datasheet

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PRODUCT SPECIFICATION
An ISR can only be interrupted by a higher priority interrupt. That is, an ISR
for a low-level interrupt can be interrupted only by a high-level interrupt. The
CPU always completes the instruction in progress before servicing an interrupt.
If the instruction in progress is RETI, or a write access to any of the IP, IE, EIP,
or EIE SFRs, the CPU completes one additional instruction before servicing the
interrupt.
The EA bit in the IE SFR (IE.7) is a global enable for all interrupts. When EA =
1, each interrupt is enabled/masked by its individual enable bit. When EA = 0,
all interrupts are masked.
flags, enables, and priorities.
Interrupt
INT0_N
TF0
INT1_N
TF1
TI or RI
TF2 or EXF2
int2
int3
int4
int5
wdti
Table 7-9 : Interrupt Flags, Enables, and Priority Control
There are two stages of interrupt priority assignment: interrupt level and natural
priority. The interrupt level (high, or low) takes precedence over natural
priority. All interrupts can be assigned either high or low priority. In addition to
an assigned priority level (high or low), each interrupt has a natural priority, as
listed in
example, both high) are resolved according to their natural priority. For
example, if INT0_N and int2 are both programmed as high priority, INT0_N
takes precedence. Once an interrupt is being serviced, only an interrupt of
higher priority level can interrupt the service routine of the interrupt currently
being serviced.
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
Table 7-8
Description
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial Port transmit or
receive
Timer 2 interrupt
ADC_EOC interrupt
SPI_READY
interrupt
RADIO.DR1 interrupt EXIF.6
RADIO.DR2 interrupt EXIF.7
RTC wakeup timer
interrupt
. Simultaneous interrupts with the same priority level (for
Table 7-9
provides a summary of interrupt sources,
QhtrÃ#'ÂsÃ(&
Flag
TCON.1
TCON.5
TCON.3
TCON.7
SCON.0 (RI),
SCON.1 (TI)
T2CON.7 (TF2),
T2CON.6 (EXF2)
EXIF.4
EXIF.5
EICON.3
Enable
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
EIE.0
EIE.1
EIE.2
EIE.3
EIE.4
Control
IP.0
IP.1
IP.2
IP.3
IP.4
IP.5
EIP.0
EIP.1
EIP.2
EIP.3
EIP.4
July 2003

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