nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 9

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
This section will give a brief overview of each of the blocks in the block diagram in
Figure 1-1.
The nRF24E1 microcontroller is instruction set compatible with the industry standard
8051. Instruction timing is slightly different from the industry standard, typically each
instruction will use from 4 to 20 clock cycles, compared with 12 to 48 for the
“standard”. The interrupt controller is extended to support 5 additional interrupt
sources; ADC, SPI, RF receiver 1, RF receiver 2 and wakeup timer. There are also 3
timers which are 8052 compatible, plus some extensions, in the microcontroller core.
An 8051 compatible UART that can use timer1 or timer2 for baud rate generation in
the traditional asynchronous modes is included. The CPU is equipped with 2 data
pointers to facilitate easier moving of data in the XRAM area, which is a common
8051 extension. The microcontroller clock is derived directly from the crystal
oscillator.
The microcontroller has a 256 byte data ram (8052 compatible, with the upper half
only addressable by register indirect addressing). A small ROM of 512 bytes, contains
a bootstrap loader that is executed automatically after power on reset or if initiated by
1
software later. The user program is normally loaded into a 4k byte RAM
from an
external serial EEPROM by the bootstrap loader. The 4k byte RAM may also
(partially) be used for data storage in some applications.
If the mask ROM option is not used, the program code for the device must be loaded
from an external non-volatile memory. The default boot loader expects this to be a
“generic 25320” EEPROM with SPI interface. These memories are available from
several vendors with supply ranges down to 1.8V. The SPI interface uses the pins
P1.2/DIN0 (EEPROM SDO), P1.0/DIO0 (EEPROM SCK), P1.1/DIO1 (EEPROM
SDI) and P0.0/DIO2 (EEPROM CSN). When the boot is completed, the P1.2/DIN0,
P1.0/DIO0 and P1.1/DIO1 pins may be used for other purposes such as other SPI
devices or GPIO.
The SFR (Special Function Registers) control several of the features of the nRF24E1.
Most of the nRF24E1 SFRs are identical to the standard 8051 SFRs. However, there
are additional SFRs that control features that are not available in the standard 8051.
The SFR map is shown in the table below. The registers with grey background are
registers with industry standard 8051 behavior. Note that the function of P0 and P1 are
somewhat different from the “standard” even if the conventional addresses (0x80 and
0x90) are used
1
Optionally this 4k block of memory can be configured as 2k mask ROM and 2k RAM or 4 k mask
ROM
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
July 2003
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