nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 51

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nRF24E1

Manufacturer Part Number
nRF24E1
Description
2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
Manufacturer
Nordic VLSI
Datasheet

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PRODUCT SPECIFICATION
This counter is used for a wakeup sometime in the future (a relative time wakeup
call). If ‘N’ is written to the counter, the first wakeup will happen from somewhere
between ‘N+1’ and ‘N+2’ “TICK” from the completion of the write, thereafter a new
wakeup is issued every “N+1” "TICK" until the unit is disabled or another value is
written to the latch.
The wakeup timer is connected to the WDTI interrupt of the CPU. The programmer
may poll the EICON.3 flag or enable the interrupt. If the oscillator is stopped, the
wakeup interrupt will restart the oscillator regardless of the state of EIE.4 interrupt
enable.
The nRF24E1 do not provide any “absolute time functions”. Absolute time functions
in nRF24E1 can well be handled in software since our RAM is continuously powered
even when in sleep mode. There will be an application note with the required code to
implement the complete absolute time function using some 100 bytes of code and 12
IRAM locations (with 2 alarms).
The watchdog is activated on the first write to its control register SFR 0xAD. It can
not be disabled by any other means than a reset. The watchdog register is loaded by
writing a 16-bit value to the two 8-bit data registers (SFR 0xAB and 0xAC) and then
the writing the correct opcode to the control register. The watchdog will then count
down towards 0 and when 0 is reached the complete microcontroller will be reset . To
avoid the reset, the software must load new values into the watchdog register
sufficiently often.
RTC and Watchdog are controlled by SFRs 0xAB, 0xAC and 0xAD. These 3 registers
REGX_MSB, REGX_LSB and REGX_CTRL are used to interface the blocks
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0
TICK
Load
REGX_CTRL
8-bit CPU
register
COUNTER
DOWN
16-BIT
Zero
REGX_MSB
8-bit CPU
register
QhtrÃ$ ÂsÃ(&
Load
Load
COUNTER
REGISTER
DOWN
16-BIT
16-BIT
REGX_LSB
8-bit CPU
register
Zero
WATCHDOG_RESET
16-BIT BUS
WAKEUP INT
July 2003

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