nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 83

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
10.9.2.3 Mode 1 Receive
Figure 18 illustrates the mode 1 receive timing. Reception begins at the falling edge of
a start bit received on rxd_in, when enabled by the REN bit.
rxd_in is sampled sixteen times per bit for any baud rate.
start bit is detected, the divide-by-16 counter used to generate the receive clock is
reset to align the counter rollover to the bit boundaries.
Figure 10-13 : Serial port Mode 1 Receive Timing
For noise rejection, the serial port establishes the content of each received bit by a
majority decision of three consecutive samples in the middle of each bit time. This is
especially true for the start bit. If the falling edge on rxd_in is not verified by a
majority decision of three consecutive samples (low), then the serial port stops
reception and waits for another falling edge on rxd_in.
At the middle of the stop bit time, the serial port checks for the following conditions:
If the above conditions are met, the serial port then writes the received byte to the
SBUF register, loads the stop bit into RB8, and sets the RI bit. If the above
conditions are not met, the received data is lost, the SBUF register and RB8 bit are not
loaded, and the RI bit is not set. After the middle of the stop bit time, the serial port
waits for another high-to-low transition on the rxd_in pin.
Mode 1 operation is identical to that of the standard 8051 when Timers 1 and 2 use
CPU_clk/12 (the default).
Mode 2 provides asynchronous, full-duplex communication, using a total of
eleven bits:
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Revision: 1.0
- RI = 0
- If SM2 = 1, the state of the stop bit is 1
- One start bit
- Eight data bits
- One programmable 9th bit
(if SM2 = 0, the state of the stop bit does not matter)
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For this purpose,
When a falling edge of a
July 2003