nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 53

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
If the Watchdog reset signal goes active, nRF24E1 enters the same reset sequence as
for power-on reset, that is the internal voltage generators and oscillators start up, the
SFRs are initialized to their reset values, as listed in Table 10-10, and thereafter the
CPU begins program execution at the standard reset vector address 0x0000. The
startup time from watchdog reset is somewhat shorter, 12 LP_OSC cycles, which in
total may vary from 2.5 to 13ms depending on processing, temperature and supply
voltage.
The program reset address is controlled by the RSTREAS register, SFR 0xB1, see
Table 8-3 This register shows which reset source that caused the last reset, and
provides a choice of two different program start addresses. The default value is power-
on reset, which starts the boot loader, while a watchdog reset does not reboot and
restarts at address 0 of the already loaded program.
Table 8-3 Reset control registe - SFR 0xB1.
nRF24E1 provides the two industry standard 8051 power saving modes: idle mode
and stop mode, but with only minor power saving; therefore also a non standard
power-down mode is provided, where both oscillator and internal power regulators are
turned off to achieve more power saving.
The bits that control entry into idle and stop modes are in the PCON register at SFR
address 0x87, listed in Table 9-1. The bits that control entry into power down mode
are in the CK_CTRL register at SFR address 0xB6, listed in Table 9-2
Bit
PCON.7
PCON.6–4
PCON.3
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
B1
R/W
Function
SMOD – Serial Port baud-rate doubler enable. When SMOD = 1, the
baud rate for Serial Port is doubled.
Reserved.
GF1 – General purpose flag 1. Bit-addressable, general purpose flag for
software control.
2
02
RSTREAS bit 0: Reason for last reset
QhtrÃ$"ÂsÃ(&
bit 1: Use IROM for reset vector
0: POR
1: Any other reset source
Clear this bit in software to force a
0: Reset vectors to 0x0000.
1: Reset vectors to 0x8000.
reboot after jump to zero (boot loader
will load code RAM if this bit is 0)
July 2003