SCAN182541ASSCX Fairchild Semiconductor, SCAN182541ASSCX Datasheet - Page 3

• Manufacturer Part Number: SCAN182541ASSCX
• Description: IC LINE DRIVER NON-INV 56SSOP
• Manufacturer: Fairchild Semiconductor
• Series: 18000r

Specifications of SCAN182541ASSCX

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Current - Output High, Low: 32mA, 15mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Logic Family: SCAN
• Number Of Channels Per Chip: 18
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 32 mA
• Low Level Output Current: 15 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 18 / 18
• Output Type: 3-State
• Propagation Delay Time: 6.5 ns at 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 10000001. The two least signifi-
Bypass Register Scan Chain Definition
Logic 0
Scan Cell TYPE1
Scan Cell TYPE2
3
cant bits of this captured value (01) are required by IEEE
Std 1149.1. The upper six bits are unique to the
SCAN18541T device. SCAN CMOS Test Access Logic
devices do not include the IEEE 1149.1 optional identifica-
tion register. Therefore, this unique captured value can be
used as a “pseudo ID” code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Instruction Register Scan Chain Definition
Instruction Code
00000000
10000001
10000010
00000011
All Others
MSB LSB
SAMPLE/PRELOAD
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Instruction
EXTEST
BYPASS
CLAMP
HIGH-Z