MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 20
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MT9M019
Manufacturer Part Number
MT9M019
Description
1/5-Inch 1.3Mp CMOS Digital Image Sensor
Manufacturer
Aptina Imaging Corporation
Datasheet
1.MT9M019.pdf
(54 pages)
Control of the Signal Interface
Serial Register Interface
Default Power-up State
Serial Pixel Data Interface
Configuration of the Pixel Data Interface
PDF: 7723845879/Source:2828556980
MT9D019_DS - Rev. F 5/10 EN
This section describes the operation of the signal interface in all functional modes.
The serial register interface uses the following signals:
• SCLK
• S
• S
SCLK is an input-only signal and must always be driven to a valid logic level for correct
operation; if the driving device can place this signal in High-Z, an external pull-up
resistor should be connected to this signal.
S
signal.
S
operation. In most applications this input will be hardwired to logic “0” if a GPI is used.
There is no dedicated S
This interface is described in detail in “Two-Wire Serial Register Interface” on page 9.
At power-up and after a hard or soft reset, the reset state of the MT9M019 is under SMIA
operation and the CCP2 high-speed serial interface.
The serial pixel data interface uses the following output-only signal pairs:
• DATAP
• DATAN
• CLKP
• CLKN
The signal pairs are driven differentially using sub-LVDS switching levels. This interface
conforms to the SMIA 1.0 CCP2 requirements and supports both data/clock signalling
and data/strobe signalling.
The DATAP , DATAN, CLKP, and CLKN pads are turned off if the SMIA serial disable bit is
asserted (R0x301A–B[12] = 1) or when the sensor is in the soft standby state.
In data/clock mode, the clock remains HIGH when no data is being transmitted. In data/
strobe mode before frame start, clock is LOW and data is HIGH.
Fields in R0x301A–B are used to configure the operation of the pixel data interface.
DATA
ADDR
DATA
ADDR
is a bidirectional signal. An external pull-up resistor should be connected on this
in an input-only signal and must always be driven to a valid logic level for correct
ADDR
pin.
20
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
Control of the Signal Interface
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