MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 25

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Table 9:
Table 10:
PDF: 7723845879/Source:2828556980
MT9D019_DS - Rev. F 5/10 EN
Valid Divisor Combinations (10 bits per pixel)
Valid Divisor Combinations (8 bits per pixel)
op_pix_clk_freq_mhz =
vt_pix_clk_freq_mhz =
PLL input clock frequency range is 2.0 –11.5 MHz.
The usage of the output clocks is shown below:
• vt_pix_clk is used by the sensor core to control the timing of the pixel array. The
• op_pix_clk is used to load parallel pixel data from the output FIFO to the CCP2 serial-
• op_sys_clk is used to generate the serial data stream on the CCP2 output. The rela-
In Profile 1,2, the output clock frequencies can be calculated as:
time equal to or less than the time defined by line_length_pck, the valid combinations
of the clock divisors are as shown in Table 9 and Table 10.
sensor core produces one 10-bit pixel each vt_pix_clk period. The line length
(line_length_pck) and fine integration time (fine_integration_time) are controlled in
increments of the vt_pix_clk period.
izer. The output FIFO generates one pixel each op_pix_clk period. The pixel is either
8-bit or 10-bit depending upon the output data format, controlled by the
ccp_data_format register (R0x0112–3).
tionship between this clock frequency and the op_pix_clk frequency is dependent
upon the output data format.
------------------------------------------------------------------------------------------------------------------- -
pre_pll_clk_div*vt_sys_clk_div*vt_pix_clk_div
---------------------------------------------------------------------------------------------------------------------- -
pre_pll_clk_div*op_sys_clk_div*op_pix_clk_div
op_sys_clk_div
op_sys_clk_div
4, 6, 8, 10
2, 4, 6, 8
18, 20
14, 16
22, 24
10
12
14
16
22
12
18
20
26
1
1
2
ext_clk_freq_mhz*pll_multiplier
ext_clk_freq_mhz*pll_multiplier
25
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
4, 5, 6, 7, 8, 9, 10
4, 5, 6, 7, 8, 9, 10
vt_pix_clk_div
vt_pix_clk_div
5, 6, 7, 8, 9, 10
5, 6, 7, 8 9, 10
6, 7, 8, 9, 10
6, 7, 8, 9, 10
4, 5, 6, 7 8
7, 8, 9, 10
7, 8, 9, 10
8, 9, 10
8, 9, 10
©2006 Aptina Imaging Corporation. All rights reserved.
9, 10
9, 10
4, 5
10
10
4
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Clocking
(EQ 1)
(EQ 2)