MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 27

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Programming the PLL Divisors
Influence of ccp_data_format
Influence of ccp2_signalling_mode
PDF: 7723845879/Source:2828556980
MT9D019_DS - Rev. F 5/10 EN
vt_pix_clk_freq_mhz =
op_pix_clk_freq_mhz =
op_sys_clk_freq_mhz =
In Profile 0 the output clock frequencies can be calculated as:
The PLL divisors should be programmed while the MT9M019 is in the software standby
state. After programming the divisors, it is necessary to wait for the VCO lock time before
enabling the PLL. The PLL is enabled by entering the streaming state.
An external timer will delay entering streaming mode by 6,750 EXTCLKs so that the PLL
can lock.
The effect of programming the PLL divisors while the MT9M019 is in the streaming state
is UNDEFINED.
The ccp_data_format register (R0x0112–3) controls whether the pixel data interface will
generate 10 bits per pixel or 8 bits per pixel. The raw output of the sensor core is 10-bits
per-pixel; the two 8-bit modes represent a compressed data mode and a mode in which
the two least significant bits of the 10-bit data are discarded.
When the pixel data interface is generating 8 bits per pixel, op_pix_clk_div must be
programmed with the value 8. When the pixel data interface is generating 10 bits per-
pixel, op_pix_clk_div must be programmed with the value 10.
The ccp2_signalling_mode register (R0x0111) controls whether the serial pixel data
interface uses data/strobe signalling or data/clock signalling.
When data/clock signalling is selected, the pll_multiplier supports both odd and even
values.
When data/strobe signalling is selected, the pll_multiplier only supports even values;
the least significant bit of the programmed value is ignored and treated as “0.”
This behavior is a result of the implementation of the CCP2 serializer and the PLL. When
the serializer is using data/strobe signalling, it uses both edges of the op_sys_clk and
therefore that clock runs at one half of the bit rate. All of the programmed divisors are set
up to make this behavior invisible. For example, when the divisors are programmed to
generate a PLL output of 640 MHz, the actual PLL output is 320 MHz but both edges are
used.
When the serializer is using data/clock signalling, it uses a single edge on the op_sys_clk
and therefore that clock runs at the bit rate.
To disguise this behavior from the programmer, the actual pll multiplier is right-shifted
by 1 bit relative to the programmed value when ccp2_signalling_mode selects data/
strobe signalling.
------------------------------------------------------------------------------------- -
pre_pll_clk_div*vt_sys_clk_div*10
------------------------------------------------------------------------------------- -
pre_pll_clk_div*vt_sys_clk_div*10
-------------------------------------------------------------------------------- -
ext_clk_freq_mhz*pll_multiplier
ext_clk_freq_mhz*pll_multiplier
ext_clk_freq_mhz*pll_multiplier
pre_pll_clk_div*vt_sys_clk_div
27
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
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Clocking
(EQ 4)
(EQ 5)
(EQ 6)