MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 24

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Clocking
Figure 12:
PDF: 7723845879/Source:2828556980
MT9D019_DS - Rev. F 5/10 EN
EXTCLK
External Input Clock
ext_clk_freq_mhz
MT9M019 SMIA Profile 1, 2 Clocking Structure
2 (1, 2, 3.....32)
Pre_pll_clk_div
Pre PLL
Divider
The MT9M019 contains a phase-locked loop (PLL) for timing generation and control.
The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to
multiply the prescaler output, and a set of dividers to generate the output clocks.
Both SMIA profile 0 clock scheme and profile 1, 2 are supported. The clocking scheme
can be selected by either setting register 0x306E–F[7] to 0 for profile 0 or to 1 for profile 1,
2.
pll_ip_clk_freq_mhz
Figure 12 shows the different clocks and (in courier font) the names of the registers
that contain or are used to control their values. The figure shows the default setting for
each divider/multipler control register and the range of legal values for each divider/
multiplier control register.
The parameter limit register space contains registers that declare the minimum and
maximum allowable values for:
• The frequency allowable on each clock
• The divisors that are used to control each clock
The following factors determine what are valid values, or combinations of valid values,
for the divider/multiplier control registers:
• The minimum/maximum frequency limits for the associated clock must be met.
• The minimum/maximum value for the divider/multiplier must be met.
• The value of pll_multiplier should be a multiple of 2.
• The op_pix_clk must never run faster than the vt_pix_clk to ensure that the CCP2
• Given the maximum programmed line length, the minimum blanking time, the
PLL Input Clock
output data stream is contiguous.
maximum image width, the available PLL divisor/multiplier values, and the require-
ment that the output line time (including the necessary blanking) must be output in a
80 (1, 2, 3.....254)
PLL_multiplier
Multiplier
PLL
pll_op_clk_freq_mhz
PLL Output Clock
24
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
op_sys_clk_div
1 (1, 2, 3.....32)
vt_sys_clk_div
op_sys _clk
vt _sys_clk
Divider
Divider
2 (2)
Video Timing System Clock
vt_sys_clk_freq_mhz
5 (4, 5, 6......10)
Aptina reserves the right to change products or specifications without notice.
vt_pic_clk_div
op_ pix _clk _ div
vt_sys_clk_freq_mhz
op_pix_clk
vt _ pix_clk
10( 8, 10)
Divider
Divider
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vt_pix_clk
op_sys_clk
op_pix_clk
Clocking