MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 28

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Programming Example
Table 11:
Clock Control
PDF: 7723845879/Source:2828556980
MT9D019_DS - Rev. F 5/10 EN
ccp2_signalling_mode
ccp_data_format
pre_pll_clk_div
op_sys_clk_div
op_pix_clk_div
vt_sys_clk_div
vt_pix_clk_div
pll_multiplier
Register
–
Default Settings
Programmed Value
This section provides one programming example which is the default settings. For this
example, a table of register values is shown (for example, Table 11, Default Settings). The
settings for the clock divisors show the "Programmed Value" and "Apparent Frequency."
These values are consistent with MT9M019 SMIA Profile 0 Clocking Structure and the
associated equations for the different clocks. The table also shows the "Effective Value"
and "Actual Frequency." These values are implementation details that reflect the
internal operation of the clocks; they are consistent with the descriptions given in “Influ-
ence of ccp_data_format” on page 27.
Example:
• 10 bits per-pixel data
• CCP2 Class 1/Class 2 signalling
• Highest possible frame rate at maximum resolution
To meet the requirement for the highest possible frame rate, vt_pix_clk should run at
64 MHz. For 10 bits per-pixel operation, op_sys_clk must run at 10x op_pix_clk. There-
fore, op_sys_clk_div is set to 1 and op_pix_clk_div to 10, giving an overall divide-by-10 in
the op clock domain. Since vt_sys_clk_div is fixed at 2, the same divide-by-10 is achieved
in the vt clock domain by setting vt_pix_clk_div to 5. As a result, the PLL output
frequency must be set to 64 * 10 = 640 MHz. There are various ways doing this,
depending upon the frequency of EXTCLK.
The register settings for this example and the resulting clock frequencies are shown in
Table 11. If the MT9M019 is programmed with these values (and all other registers are
left at their default values), and is then put into streaming mode (mode_select=1) it will
stream frames at full resolution (1,280 x 1,024 pixels) through its CCP2 interface at
31.1 fps.
The MT9M019 uses an aggressive clock-gating methodology to reduce power consump-
tion. The clocked logic is divided into a number of separate domains, each of which is
only clocked when required.
When the MT9M019 enters a low-power state, almost all of the internal clocks are
stopped. The only exception is that a small amount of logic is clocked so that two-wire
serial interface continues to respond to read and write requests.
0x0A0A
80
10
1
–
2
2
5
1
Data/strobe signalling
10 bits per pixel
Effective Value
40
–
2
1
5
1
5
28
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
op_sys_clk
op_pix_clk
pll_op_clk
vt_sys_clk
vt_pix_clk
pll_ip_clk
EXTCLK
Clock
–
–
Aptina reserves the right to change products or specifications without notice.
Frequency
Apparent
640 MHz
320 MHz
640 MHz
16 MHz
64 MHz
64 MHz
©2006 Aptina Imaging Corporation. All rights reserved.
8 MHz
-–
–
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Frequency
320 MHz
320 MHz
320 MHz
16 MHz
64 MHz
64 MHz
Actual
8 MHz
Clocking
–
–