MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 26

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Figure 13:
PDF: 7723845879/Source:2828556980
MT9D019_DS - Rev. F 5/10 EN
EXTCLK
ext_clk_freq_mhz
External Input Clock
MT9M019 SMIA Profile 0 Clocking Structure
Pre_pll_clk_div
op_sys_clk_freq_mhz =
(1,2,4)
Pre PLL
Divider
Figure 13 shows the different clocks and (in courier font) the names of the registers
that contain or are used to control their values. Figure 13 shows the default setting for
each divider/multipler control register and the range of legal values for each divider/
multiplier control register.
The parameter limit register space contains registers that declare the minimum and
maximum allowable values for:
• The frequency allowable on each clock.
• The divisors that are used to control each clock.
The following factors determine what are valid values, or combinations of valid values,
for the divider/multiplier control registers:
• The minimum/maximum frequency limits for the associated clock must be met.
• The minimum/maximum value for the divider/multiplier must be met.
• Given the maximum programmed line length, the minimum blanking time, the
PLL input clock frequency range is 2.0 –11.5 MHz.
The usage of the output clocks is shown below:
• vt_pix_clk is used by the sensor core to control the timing of the pixel array. The
• vt_sys_clk is also used to generate the serial data stream on the CCP2 output.
pll_ip_clk_freq_mhz
maximum image width, the available PLL divisor/multiplier values, and the require-
ment that the output line time (including the necessary blanking) must be output in a
time equal to or less than the time defined by line_length_pck.
sensor core produces one 10-bit pixel each vt_pix_clk period. The line length
(line_length_pck) and fine integration time (fine_integration_time) are controlled in
increments of the vt_pix_clk period.
PLL Input Clock
80 (1,2,3....254)
PLL_multiplier
Multiplier
PLL
pll_op_clk_freq_mhz
-------------------------------------------------------------------------------- -
pre_pll_clk_div*op_sys_clk_div
ext_clk_freq_mhz*pll_multiplier
PLL Output Clock
26
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
(1,2,3,4,6,8....)
vt_sys_clk_div
vt_sys_ clk
Divider
Video Timing System Clock
vt_sys_clk_freq_mhz
Aptina reserves the right to change products or specifications without notice.
vt_pix_clk_div
vt_pix_clk
10 (10)
Divider
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op_sys_clk
vt_pix_clk
Clocking
(EQ 3)