AN2168 Freescale Semiconductor / Motorola, AN2168 Datasheet
AN2168
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AN2168 Summary of contents
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... Order this document by AN2168/D Semiconductor Products Sector Application Note ColdFire Microprocessor DMA Controller By Melissa Hunter Austin, Texas Introduction This application note discusses the use of the DMA (direct memory access) module available on several of the ColdFire processors. This list includes the MCF5206e, MCF5307, and MCF5407. The DMA modules on all three of these processors are very similar, and most of the information in this application note can be applied to all three ...
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... The timing, control signals, and strobes will be the same, only the transfer type and transfer modifier information will be different the DMA source or destination address “hits” chip select space, then the chip select control registers will define the bus cycle (wait states, bursting, etc.). 2 AN2168 MOTOROLA ...
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... For example, to address 0xFFE00400. Figure 1. Chip Select-Initiated Bus Cycle AN2168 MOTOROLA What Do DMA Bus Cycles Look Like? Figure 1 shows a software-initiated, word-sized bus cycle Application Note 3 ...
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... DMA can be used to transfer large blocks of data more efficiently than the core itself. 4 shows another word-sized bus cycle to 0xFFE00400. The chip Figure 2. DMA-Initiated Bus Cycle there are two dead clocks after the deassertion of the chip Figure 2 there are no dead AN2168 MOTOROLA ...
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... The DMA is programmed with the following values: DSR = 0x01 ; clear status register SAR = 0xFFE00400 ; source address = 0xFFE00400 DAR = 0x20000000 ; destination address = 0x20000000 BCR = 0x002 ; transfer 2 bytes DCR = 0x006B ; source = 16-bit, destination = 8-bit AN2168 MOTOROLA Dual address Single address Application Note Dual and Single Address Modes ...
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... The DMA controller needs to write the full 16 bits of data to the destination, so the read is followed by two byte-size transfers to the destination address. Figure 3. Dual Address Transfer, SSIZE = word, DSIZE = byte 6 shows the resulting dual address DMA transfer. Since the AN2168 MOTOROLA ...
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... Since CS1 is programmed to allow bursts and the DMA requests a transfer size larger than the chip select’s port size, a burst transfer results. Figure 4. Dual Address Transfer, SSIZE = word, DSIZE = word AN2168 MOTOROLA Dual Address Mode Example 1 shows the DMA transfer with the source and destination both ...
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... BCR = 0x0002 ; transfer 2 bytes DCR = 0x01D1 ; single address, R source=8-bit 8 does not take advantage of the fact that CS1 is programmed only takes 10 clock cycles to transfer the same amount of data. shows a single address transfer to address 0x20000000 using Dual Address Mode Figure 3 takes AN2168 MOTOROLA ...
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... In this example, the chip select is programmed for a zero wait state 8-bit port. The DMA is set up for 8-bit single address transfers with R/W high. AN2168 MOTOROLA Figure 5. Single Address Transfer, SSIZE = byte Application Note Dual and Single Address Modes 9 ...
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... A multiple of the BWC value is reached — The DMA will release the bus when the BCR reaches a multiple of the value programmed into the BWC. The transfer completes — The BCR reaches zero, the DMA terminates with an error, or the DONE bit is set by software (internal request only). Internal requests External requests AN2168 MOTOROLA ...
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... CSMR0 = 0x000F0001 ; address range = 0xFFE00000-0xFFEFFFFF CSCR0 = 0x0D80 ; 3 waitstates, autoacknowledge, 16-bit port CSAR1 = 0x2000 ; base address = 0x20000000 CSMR1 = 0x00000001 ; address range = 0x20000000-0x2000FFFF CSCR1 = 0x0158 ; 0 waitstates, autoacknowledge, 8-bit port, burst enabled AN2168 MOTOROLA and Figure 7 show a cycle steal DMA transfer using the Application Note ...
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... DSR = 0x01 ; clear status register SAR = 0xFFE00400 ; source address = 0xFFE00400 DAR = 0x20000000 ; destination address = 0x20000000 BCR = 0x0004 ; transfer 4 bytes DCR = 0x606A ; cycle steal, ext. request, source=16-bit, destination=8-bit Figure 6. Cycle Steal Transfer Using External Request Mode — AN2168 MOTOROLA ...
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... BCR decrements by two again, clearing the BCR. This signals the end of the entire DMA transfer and the DONE bit in the DSR is set. Finally, bus mastership returns to the core and a normal mode access is started. AN2168 MOTOROLA shows the first word transfer of the DMA cycle. Cursor 1 marks Dual Address Mode Example shows the transfer of the second word ...
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... DSR = 0x01 ; clear status register SAR = 0xFFE00001 ; source address = 0xFFE00001 DAR = 0x20000000 ; destination address = 0x20000000 BCR = 0x0004 ; transfer 4 bytes DCR = 0x106B ; auto-align, source=16-bit, destination=8-bit Figure 8 14 and the DMA registers settings that follow would give shows the actual transfer. Dual Address AN2168 MOTOROLA ...
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... Now there is only one byte remaining to be transferred (BCR = 1), so there is a byte read from the source and a byte write to the destination to complete the DMA transfer. AN2168 MOTOROLA Application Note Auto-alignment ...
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... UART receive buffer (URB) and the source increment option is disabled. Refer to NOTE: The MCF5206e cannot DMA to or from the UARTs. The MCF5307 and MCF5407 can DMA from the UARTs, but not to the UARTs. 16 DMA from UART Example for assembly example code. AN2168 MOTOROLA ...
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... DMA channel will reassert the bus request to the internal arbiter. Once the internal arbiter gives mastership of the external bus back to the DMA channel, the transfer will resume and continue until the byte count decrements to zero. AN2168 MOTOROLA Application Note Bandwidth Control ...
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... DMA interrupt occurs, the DMA will return the value in the DIVR. Then the processor will start the exception handling process by building the exception stack frame and fetching the vector table entry specified by the DIVR. Refer to 18 Programming the DIVR Using the autovector feature DMA Interrupt Example for a software example. AN2168 MOTOROLA ...
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... This can be done in two steps. First, set the pin assignment register (PAR) bit 3 and/or bit 2 to enable the transfer modifier and DACK functionality. Then set one or both of the ENBDACKn bits in the interrupt port assignment register (IRQPAR). AN2168 MOTOROLA Application Note DACK Generation ...
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... DACK will assert for every transfer (default that DACK is asserted only during the final read and/or write of the entire DMA transfer. NOTE: The AT bit is only available on the MCF5307 when the BCR24BIT in the bus master park register (MPARK) is set. 20 AN2168 MOTOROLA ...
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... BUS REQUEST FOR AT LEAST ONE CLOCK. THEN REASSERT REQUEST FOR MASTERSHIP OF EXTERNAL BUS. Figure 9. Dual Address Mode DMA Flowchart AN2168 MOTOROLA DMA PROGRAMMED, REQUEST (INTERNAL OR EXTERNAL) RECEIVED, AND DMA GRANTED MASTERSHIP OF EXTERNAL BUS DMA READ PHASE BUS CYCLE(S) FROM SOURCE ADDRESS ...
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... MASTERSHIP OF EXTERNAL BUS DMA READ PHASE BUS CYCLE(S) FROM SOURCE ADDRESS Y ERROR SINC = 1? N BCR DECREMENTED Y BCR = CYCLE STEAL BCR = MULTIPLE OF BWC? N BUS ERROR ON SOURCE (BES) AND DONE BITS SET IN DSR SAR INCREMENTED SET DONE BIT IN DSR AN2168 MOTOROLA ...
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... DIVR2 equ MBAR+0x394 ; UART0 defines UMR equ MBAR+0x1C0 UCSR equ MBAR+0x1C4 UCR equ MBAR+0x1C8 URB equ MBAR+0x1CC UACR equ MBAR+0x1D0 UIMR equ MBAR+0x1D4 UBG1 equ MBAR+0x1D8 UBG2 equ MBAR+0x1DC .align 0x10 XDEF _main AN2168 MOTOROLA Application Note DMA from UART Example 23 ...
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... UMR2 (UART0 mode register) ;for normal mode, 1 stop bit ;the transmitter and receiver are both ;clocked using the system bus clock (BCLKO) ;Disable interrupts for the COS & /CTS ;enabled receiver interrupt ;program dividers for 19200 baud rate AN2168 MOTOROLA ...
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... The code runs from address 0x20000000, so internal SRAM or other ; memory needs to be mapped to this region. org $100 DMA_VECTOR: AN2168 MOTOROLA ;enable transmitter ;enable receiver ;clear the DMA status register ...
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... MBAR equ 0x10000000 RAMBAR equ 0x20000000 VBR equ 0x00000000 ICR6 equ MBAR+0x052 IMR equ MBAR+0x044 SAR0 equ MBAR+0x300 DAR0 equ MBAR+0x304 DCR0 equ MBAR+0x308 BCR0 equ MBAR+0x30C 26 AN2168 MOTOROLA ...
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... DCR0,d0 bset.l #0,d0 move.w d0,DCR0 AN2168 MOTOROLA ;Reset SR. Interrupts ;possible at levels 0-7 ;define the init location of the ;Vector Base register ;set DMA ICR for level 2, priority 0 ;enable DMA0 interrupt in IMR ;program the DIVR to return vector 40 in ...
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... ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/ ;idle loop ;clear the DMA status register ;to clear the interrupt condition ;return from exception are registered trademarks of Motorola, Inc. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc., 2001 AN2168/D ...