AN2168 Freescale Semiconductor / Motorola, AN2168 Datasheet - Page 17

• Manufacturer Part Number: AN2168
• Description: ColdFire Microprocessor DMA Controller Application Note
• Manufacturer: Freescale Semiconductor / Motorola

Bandwidth Control
Bandwidth Control
Example
AN2168
MOTOROLA
When a continuous mode DMA transfer (internal or external request) is
started, the DMA must assert a request to the processor’s internal arbiter
to gain mastership of the external bus. Once the internal arbiter grants
the channel mastership of the bus, the DMA transfer will begin. The DMA
module has a bandwidth control feature that can help to prevent the
DMA from choking off the core’s access to the external bus. The
bandwidth control settings programmed in the DCR[BWC] can be used
to force the DMA to relinquish control of the external bus at certain
intervals and thereby allow the core an opportunity to gain mastership of
the external bus.
When a multiple of the BWC has been reached, the DMA channel will
relinquish the bus by negating its request to the internal arbiter for one
clock. At this point, the core or another DMA channel can gain
mastership of the bus. One clock later the DMA channel will request the
bus again so that it can complete the transfer. The DMA channel will
have to go through the arbiter to gain mastership of the bus again. If a
higher priority master is also requesting the bus, then the DMA cycle will
be delayed while waiting for the arbiter to grant bus mastership to the
DMA channel.
For example, if the DCR[BWC] bits are set for 512 bytes, then every time
the BWC reaches a value that is a multiple of 512 the DMA will negate
its request to the internal arbiter for one clock. If the byte count for the
entire transfer is set to 1000 bytes and the DMA transfers one byte at a
time (source and destination size are both byte), then after the first 488
bytes are transferred the BCR will equal 512 and the DMA will negate its
bus request. Since the DMA channel still has another 512 bytes left to
move, the DMA transfer is not complete. After the request is negated for
one clock, the DMA channel will reassert the bus request to the internal
arbiter. Once the internal arbiter gives mastership of the external bus
back to the DMA channel, the transfer will resume and continue until the
byte count decrements to zero.
Bandwidth Control
Application Note
17