AN2168 Freescale Semiconductor / Motorola, AN2168 Datasheet - Page 19

• Manufacturer Part Number: AN2168
• Description: ColdFire Microprocessor DMA Controller Application Note
• Manufacturer: Freescale Semiconductor / Motorola

Autovectoring
DACK Generation
MCF5206e DACK
Generation
MCF5307 DACK
Generation
MCF5407 DACK
Generation
AN2168
MOTOROLA
The second option is using the ColdFire interrupt controller’s autovector
feature. Setting the AVEC bit in the appropriate interrupt control register
(ICR) will enable autovectoring for interrupts generated by the
corresponding module. The autovector feature allows the interrupt
controller to generate a vector for the interrupt based on the interrupt
level. Instead of using the vector returned during the internal IACK cycle,
the interrupt controller will discard this value and use a vector equal to
24 plus the interrupt level.
In some cases, in particular when using an external DMA request, it is
helpful to have a DMA acknowledge signal that indicates when a DMA
cycle occurs. The method to generate a DACK can vary from processor
to processor, so each part is covered separately.
The MCF5206e does not generate any type of DACK, so external logic
is needed. The DACK can be generated by monitoring the TT[1:0] pins.
A TT[1:0] encoding of 01 indicates a DMA bus cycle, then the address
or chip selects can be used to determine which DMA channel is
accessing the bus. If only one DMA channel is used, then the external
logic can be simplified to only monitor the TT[1:0] lines.
For the MCF5307, the TM[2:0] pins do indicate DACKs; however, these
are not dedicated DACK pins. They only indicate a DACK when the
TT[1:0] = 01 designating a DMA access, so external logic will be needed
to qualify the transfer modifier signals based on the transfer type
encoding.
The MCF5407 generates DACK signals. In this case, the DACK pins are
multiplexed with other functions, so the DACK functionality must be
enabled. This can be done in two steps. First, set the pin assignment
register (PAR) bit 3 and/or bit 2 to enable the transfer modifier and DACK
functionality. Then set one or both of the ENBDACKn bits in the interrupt
port assignment register (IRQPAR).
DACK Generation
Application Note
19