AN2168 Freescale Semiconductor / Motorola, AN2168 Datasheet - Page 11

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AN2168

Manufacturer Part Number
AN2168
Description
ColdFire Microprocessor DMA Controller Application Note
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Internal Requests
External Requests
External Request,
Cycle Steal Mode
Example
AN2168
MOTOROLA
CSAR0 = 0xFFE0 ; base address = 0xFFE00000
CSMR0 = 0x000F0001 ; address range = 0xFFE00000-0xFFEFFFFF
CSCR0 = 0x0D80 ; 3 waitstates, autoacknowledge, 16-bit port
CSAR1 = 0x2000 ; base address = 0x20000000
CSMR1 = 0x00000001 ; address range = 0x20000000-0x2000FFFF
CSCR1 = 0x0158 ; 0 waitstates, autoacknowledge, 8-bit port, burst enabled
NOTE:
For an internal request, software sets the DCR[START] bit to begin a
DMA cycle. Using internal DMA requests is straightforward. Since the
DMA is started by software, there aren’t any timing concerns to worry
about.
However, be careful when setting the DCR[START] if the DCR[EEXT] is
also set, since this could lead to conflicts with an incoming external
request.
All of the previous examples in this application note have used an
internal request to start the DMA transfer.
A DMA transfer also can be requested by asserting the DREQx line. To
have an external request start a DMA transfer, the DCR[EEXT] must be
set; otherwise, the assertion of DREQx will be ignored.
At a minimum, DREQx should be asserted for one rising clock edge (it
will also need to meet the setup and hold time requirements with respect
to the clock edge). The maximum time DREQx can be held depends on
the configuration. In continuous mode, DREQx should be deasserted
before the end of the DMA transfer.
However, in cycle steal mode, the DREQx must be negated early
enough or additional unwanted transfers could occur. If you are using
dual address cycle steal mode and only want one DMA transfer, then
DREQx should be negated before the write portion of the transfer starts.
For single address cycle steal mode, DREQx must negate before the
DMA transfer starts to prevent additional transfers from occurring.
Figure 6
external request mode. This example uses the following chip select
settings:
and
Figure 7
show a cycle steal DMA transfer using the
Application Note
Request Modes
11

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